openhwgroup / core-v-polara-apu
The OpenPiton Platform
☆16Updated 8 months ago
Alternatives and similar repositories for core-v-polara-apu:
Users that are interested in core-v-polara-apu are comparing it to the libraries listed below
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- ☆25Updated 2 weeks ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- ☆57Updated this week
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆23Updated 6 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆51Updated 3 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 2 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 10 months ago
- RISC-V Nox core☆62Updated last month
- ☆35Updated 3 weeks ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆95Updated last month
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- ☆31Updated 3 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- An energy-efficient RISC-V floating-point compute cluster.☆74Updated last week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆81Updated last year
- ☆92Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 4 months ago
- Library of open source Process Design Kits (PDKs)☆39Updated last week
- matrix-coprocessor for RISC-V☆14Updated this week
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆24Updated last week
- A SystemVerilog source file pickler.☆56Updated 6 months ago