openhwgroup / core-v-polara-apu
The OpenPiton Platform
☆15Updated 3 months ago
Related projects ⓘ
Alternatives and complementary repositories for core-v-polara-apu
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- RISC-V Matrix Specification☆15Updated 2 months ago
- SystemVerilog frontend for Yosys☆46Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆60Updated this week
- DUTH RISC-V Superscalar Microprocessor☆28Updated 3 weeks ago
- ☆29Updated 2 months ago
- ☆37Updated 5 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- Advanced Architecture Labs with CVA6☆49Updated 10 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆73Updated 7 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆138Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 8 months ago
- ☆21Updated 2 months ago
- ☆75Updated last year
- Open source RTL simulation acceleration on commodity hardware☆22Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- A configurable SRAM generator☆40Updated this week
- HLS for Networks-on-Chip☆31Updated 3 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆33Updated last year
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated last month
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆29Updated 5 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆75Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆23Updated this week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week