The OpenPiton Platform
☆17Aug 14, 2024Updated last year
Alternatives and similar repositories for core-v-polara-apu
Users that are interested in core-v-polara-apu are comparing it to the libraries listed below
Sorting:
- RISC-V processor☆32May 26, 2022Updated 3 years ago
- CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform☆13Nov 12, 2023Updated 2 years ago
- A reliable, real-time subsystem for the Carfield SoC☆19Dec 2, 2025Updated 3 months ago
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆22Nov 21, 2020Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20May 4, 2017Updated 8 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆26Aug 16, 2023Updated 2 years ago
- ☆34Feb 17, 2026Updated 2 weeks ago
- RISC-V Nox core☆71Jul 22, 2025Updated 7 months ago
- Contains commonly used UVM components (agents, environments and tests).☆32Aug 17, 2018Updated 7 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Jul 22, 2025Updated 7 months ago
- ☆33Jan 7, 2025Updated last year
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆101Feb 20, 2026Updated 2 weeks ago
- ☆46Dec 10, 2025Updated 2 months ago
- ☆13Aug 7, 2025Updated 7 months ago
- This repo contains instructions, benchmarks, and files for running user space networking in gem5 simulator.☆12Aug 1, 2024Updated last year
- ☆15Feb 15, 2022Updated 4 years ago
- LuxCoreRender Windows Compilation Environment☆13Jun 3, 2024Updated last year
- ☆12Apr 15, 2025Updated 10 months ago
- Fast Sparse Multifrontal Solver☆11May 27, 2015Updated 10 years ago
- Advanced Integrated Circuits 2025☆13Nov 1, 2025Updated 4 months ago
- Original RISC-V 1.0 implementation. Not supported.☆42Oct 4, 2018Updated 7 years ago
- BlackParrot on Zynq☆52Feb 11, 2026Updated 3 weeks ago
- An energy-efficient RISC-V floating-point compute cluster.☆124Updated this week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆169Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆197Mar 2, 2026Updated last week
- ☆11Mar 22, 2022Updated 3 years ago
- SOLID principles using modern C++☆10Dec 11, 2021Updated 4 years ago
- Tools for SystemVerilog development.☆15Jan 3, 2018Updated 8 years ago
- r2live相关论文、代码中文注释以及代码改动☆11Sep 24, 2021Updated 4 years ago
- PyBitmessage API frontend for Android using QT5 and python 3☆12Oct 3, 2018Updated 7 years ago
- ☆12Apr 25, 2025Updated 10 months ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 8 years ago
- Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Da…☆26Updated this week
- The RAS Error-record Register Interface provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting …☆11Mar 1, 2026Updated last week
- biRISC-V - 32-bit dual issue RISC-V CPU Software Environment☆15Jun 24, 2021Updated 4 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago