openhwgroup / core-v-polara-apu
The OpenPiton Platform
☆16Updated 9 months ago
Alternatives and similar repositories for core-v-polara-apu
Users that are interested in core-v-polara-apu are comparing it to the libraries listed below
Sorting:
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆72Updated 3 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- ☆27Updated last month
- ☆31Updated 4 months ago
- ☆38Updated last month
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 2 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆56Updated 3 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- matrix-coprocessor for RISC-V☆14Updated 3 weeks ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆40Updated 2 years ago
- ☆61Updated this week
- Library of open source Process Design Kits (PDKs)☆40Updated last week
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆54Updated 3 years ago
- A SystemVerilog source file pickler.☆56Updated 6 months ago
- Advanced Architecture Labs with CVA6☆59Updated last year
- HLS for Networks-on-Chip☆34Updated 4 years ago
- YosysHQ SVA AXI Properties☆39Updated 2 years ago
- An open source generator for standard cell based memories.☆13Updated 8 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆11Updated 6 months ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆36Updated this week
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆23Updated 6 years ago
- Open Source PHY v2☆28Updated last year
- A configurable SRAM generator☆48Updated 4 months ago
- ☆36Updated 2 years ago