openhwgroup / core-v-polara-apu
The OpenPiton Platform
☆17Updated 7 months ago
Alternatives and similar repositories for core-v-polara-apu:
Users that are interested in core-v-polara-apu are comparing it to the libraries listed below
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆51Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆68Updated this week
- ☆24Updated last month
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆21Updated 6 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆70Updated this week
- ☆20Updated 5 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last month
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated 2 months ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated last year
- Reconfigurable Binary Engine☆16Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆80Updated last week
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 10 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 3 months ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆34Updated 4 years ago
- ☆50Updated this week
- BlackParrot on Zynq☆33Updated 3 weeks ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 3 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last month
- RISC-V Nox core☆62Updated 8 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆31Updated 3 weeks ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- ☆25Updated last year
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆15Updated 10 months ago
- Advanced Architecture Labs with CVA6☆55Updated last year