Fraunhofer-IMS / airisc_core_complex
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
☆85Updated last year
Alternatives and similar repositories for airisc_core_complex:
Users that are interested in airisc_core_complex are comparing it to the libraries listed below
- A demo system for Ibex including debug support and some peripherals☆61Updated 5 months ago
- ☆76Updated last month
- RISC-V Verification Interface☆84Updated this week
- ☆103Updated 3 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated last week
- Basic RISC-V Test SoC☆112Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 2 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆160Updated 3 months ago
- ☆53Updated 4 years ago
- RISC-V System on Chip Template☆156Updated this week
- Open-source high performance AXI4-based HyperRAM memory controller☆65Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆172Updated last year
- Arduino compatible Risc-V Based SOC☆144Updated 7 months ago
- FuseSoC standard core library☆126Updated 3 weeks ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆51Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆113Updated 2 months ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆49Updated 5 years ago
- ☆72Updated 5 months ago
- A Fast, Low-Overhead On-chip Network☆169Updated last week
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆150Updated 2 years ago
- round robin arbiter☆70Updated 10 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆160Updated this week
- Fabric generator and CAD tools☆160Updated last week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 3 years ago
- Vector processor for RISC-V vector ISA☆113Updated 4 years ago