Fraunhofer-IMS / airisc_core_complex

Related projects ⓘ

Alternatives and complementary repositories for airisc_core_complex

• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆57Updated 3 weeks ago
• pulp-platform / pulp-sdk
  ☆99Updated 9 months ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆67Updated 4 months ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆140Updated last year
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆54Updated 2 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆31Updated 3 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆79Updated last year
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆134Updated 2 weeks ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆153Updated this week
• oprecomp / DDR4_controller
  ☆46Updated 3 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆104Updated 5 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆77Updated 3 months ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆136Updated 3 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆74Updated 2 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆61Updated last year
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆97Updated 4 years ago
• lowRISC / ariane-ethernet
  open-source Ethenet media access controller for Ariane on Genesys-2
  ☆18Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 5 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆41Updated 2 weeks ago
• xupgit / Advanced-Embedded-System-Design-Flow-on-Zynq
  ☆50Updated 5 years ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆165Updated 5 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆156Updated 2 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆109Updated 4 months ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆69Updated last year
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆57Updated 2 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆168Updated 9 months ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆120Updated 10 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆51Updated last year
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆72Updated 2 months ago