Alternatives and similar repositories for airisc_core_complex

Users that are interested in airisc_core_complex are comparing it to the libraries listed below

• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated 10 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆123Updated 4 months ago
• pulp-platform / pulp-sdk
  ☆120Updated this week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆151Updated this week
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆79Updated last week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated last month
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆159Updated 6 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆96Updated 2 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated last year
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆157Updated last year
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆181Updated 11 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 2 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆125Updated 6 months ago
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆177Updated 6 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆119Updated this week
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 3 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆116Updated 4 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated last month
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 6 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆95Updated 4 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆115Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated last week
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆79Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 2 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆86Updated 4 years ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆93Updated last year
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆91Updated 10 months ago
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆51Updated last month
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago