Fraunhofer-IMS / airisc_core_complexLinks
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
☆96Updated 3 months ago
Alternatives and similar repositories for airisc_core_complex
Users that are interested in airisc_core_complex are comparing it to the libraries listed below
Sorting:
- A demo system for Ibex including debug support and some peripherals☆78Updated 3 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 2 months ago
- ☆118Updated last week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆70Updated 9 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆140Updated last month
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated 11 months ago
- ☆95Updated last month
- RISC-V Verification Interface☆107Updated last week
- RISC-V System on Chip Template☆159Updated last month
- Arduino compatible Risc-V Based SOC☆156Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated last week
- RISC-V Nox core☆68Updated 2 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- Basic RISC-V Test SoC☆144Updated 6 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆66Updated 2 weeks ago
- RISC-V Integration for PYNQ☆176Updated 6 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆78Updated 4 years ago
- ASIC implementation flow infrastructure☆125Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated 2 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆47Updated this week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 3 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆116Updated this week
- General Purpose AXI Direct Memory Access☆59Updated last year
- Simple single-port AXI memory interface☆46Updated last year
- BlackParrot on Zynq☆47Updated 7 months ago