Fraunhofer-IMS / airisc_core_complexLinks
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
☆91Updated last year
Alternatives and similar repositories for airisc_core_complex
Users that are interested in airisc_core_complex are comparing it to the libraries listed below
Sorting:
- A demo system for Ibex including debug support and some peripherals☆67Updated last week
- ☆86Updated 2 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 6 months ago
- ☆111Updated last week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆110Updated 2 weeks ago
- Basic RISC-V Test SoC☆128Updated 6 years ago
- RISC-V Verification Interface☆92Updated this week
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last week
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆88Updated 5 months ago
- Control and Status Register map generator for HDL projects☆116Updated last week
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated this week
- A Fast, Low-Overhead On-chip Network☆207Updated this week
- ☆135Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆47Updated 7 months ago
- Fabric generator and CAD tools.☆185Updated last week
- UART -> AXI Bridge☆61Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆89Updated this week
- SpinalHDL Hardware Math Library☆86Updated 10 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated 3 weeks ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆186Updated this week
- General Purpose AXI Direct Memory Access☆50Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆147Updated 11 months ago