Alternatives and similar repositories for airisc_core_complex:

Users that are interested in airisc_core_complex are comparing it to the libraries listed below

• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆60Updated 4 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆61Updated 3 weeks ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆74Updated last week
• oprecomp / DDR4_controller
  ☆50Updated 3 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆157Updated 2 months ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆76Updated last year
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆32Updated 3 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆108Updated 5 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆64Updated 9 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆44Updated 2 months ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆61Updated 4 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆44Updated last week
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆99Updated 3 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆49Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 8 months ago
• openhwgroup / cve2
  The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…
  ☆32Updated this week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆138Updated 7 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆82Updated 4 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆57Updated last month
• pulp-platform / pulp-sdk
  ☆102Updated 11 months ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆84Updated 2 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆130Updated last month
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆144Updated 6 months ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆53Updated 2 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆155Updated this week
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆51Updated 2 years ago
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆81Updated 2 weeks ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆39Updated last year
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆61Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆48Updated this week