QmppmQ / riscv

Related projects ⓘ

Alternatives and complementary repositories for riscv

• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆14Updated 3 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆40Updated this week
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆39Updated 2 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆18Updated 3 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆16Updated 2 years ago
• fffasttime / AnyPackingNet
  ☆24Updated 8 months ago
• kuladeepsaireddy / OpenNoc
  ☆26Updated 5 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆69Updated 2 years ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆14Updated last year
• gl9544 / vit_transformer_fpga
  ☆13Updated last year
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆11Updated 3 months ago
• gem5-X / TiC-SAT
  ☆10Updated 5 months ago
• yportne13 / SpinalResNet
  AdderNet ResNet20 for cifar10 written in SpinalHDL
  ☆33Updated 3 years ago
• Zhu-Zixuan / Bitlet-PE
  A bit-level sparsity-awared multiply-accumulate process element.
  ☆12Updated 4 months ago
• CASR-HKU / DPACS
  ☆18Updated last year
• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆10Updated 3 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆65Updated 3 years ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆73Updated 2 years ago
• sharc-lab / FPGA_ECE8893
  ☆30Updated 2 months ago
• Qingchuan-Ma / IC-designer
  note about IC knowledge
  ☆9Updated 2 years ago
• gicLAB / SECDA
  ☆18Updated last year
• albertomarchisio / SwiftTron
  ☆37Updated last year
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆32Updated 2 months ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆30Updated last month
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆57Updated 2 months ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆20Updated last year
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆32Updated last year
• maomran / softmax
  Verilog implementation of Softmax function
  ☆48Updated 2 years ago