LSTM neural network (verilog)
☆16Dec 5, 2018Updated 7 years ago
Alternatives and similar repositories for LSTM
Users that are interested in LSTM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆32May 20, 2020Updated 5 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 4 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆19Jul 9, 2024Updated last year
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆18Feb 16, 2024Updated 2 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆25Jun 28, 2019Updated 6 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 8 years ago
- BlockCIrculantRNN (LSTM and GRU) using TensorFlow☆14Oct 30, 2018Updated 7 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆14Nov 4, 2022Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- Using LSTM ,GNN and GCN for Predicition of Taxi Demand. / 使用LSTM, GNN 和 GCN 解决出租车需求预测问题☆22Jan 16, 2024Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆13Mar 30, 2023Updated 3 years ago
- AFP is a hardware-friendly quantization framework for DNNs, which is contributed by Fangxin Liu and Wenbo Zhao.☆13Nov 8, 2021Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Design some simple RISV-V cores via verilog and vivado. 复旦大学《计算机与智能处理器体系结构 AI Core and RISC Architecture》Projects☆15Jun 28, 2021Updated 4 years ago
- Resource Utilization and Latency Estimation for ML on FPGA.☆18Apr 11, 2026Updated 3 weeks ago
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆22May 27, 2024Updated last year
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆17Sep 9, 2023Updated 2 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- Verilog library for implementing neural networks.☆27Aug 19, 2014Updated 11 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- 关于数字IC的笔试面试题☆15Nov 17, 2019Updated 6 years ago
- Hyperdimensional computing for language recognition: Matlab and RTL implementations☆36Jan 28, 2017Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- 第三届FPGA创新大赛-加速视觉处理小组☆16Nov 25, 2019Updated 6 years ago
- Synthesizable SystemVerilog IP-Core of the I2S Receiver☆10Jun 7, 2020Updated 5 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- Systolic-array based Deep Learning Accelerator generator☆29Dec 11, 2020Updated 5 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆26Apr 5, 2018Updated 8 years ago
- ☆10Nov 5, 2019Updated 6 years ago
- Fully Hardware-Based Stochastic Neural Network☆22Jan 23, 2025Updated last year
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Jan 12, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- 使用FPGA实现CNN模型☆15Jun 21, 2019Updated 6 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- verilog CNN generator for FPGA☆34Jan 4, 2021Updated 5 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆22Nov 9, 2025Updated 5 months ago
- ☆13Mar 5, 2024Updated 2 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- ☆18Sep 28, 2017Updated 8 years ago