niexun / LSTM
LSTM neural network (verilog)
☆13Updated 6 years ago
Alternatives and similar repositories for LSTM:
Users that are interested in LSTM are comparing it to the libraries listed below
- EE 272B - VLSI Design Project☆11Updated 3 years ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆30Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆9Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 4 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆10Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆14Updated 3 years ago
- CNN accelerator using NoC architecture☆15Updated 6 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆32Updated 5 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆26Updated 5 years ago
- Feed-forward neural networks can be trained based on a gradient-descent based backpropagation algorithm. But, these algorithms require mo…☆12Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆27Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- ☆14Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆22Updated 2 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- This repository contains full code of Softmax Layer in Verilog☆16Updated 4 years ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆22Updated 5 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆9Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- ☆9Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆23Updated 4 years ago
- ☆24Updated 5 years ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆40Updated 5 months ago
- MulApprox - A comprehensive library of state-of-the-art approximate multipliers☆20Updated 3 years ago