OpenXuantie - OpenC906 Core
☆417Jun 28, 2024Updated 2 years ago
Alternatives and similar repositories for openc906
Users that are interested in openc906 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OpenXuantie - OpenE906 Core☆177Jun 28, 2024Updated 2 years ago
- OpenXuantie - OpenC910 Core☆1,476Jun 28, 2024Updated 2 years ago
- OpenXuantie - OpenE902 Core☆179Jun 28, 2024Updated 2 years ago
- Yocto project for Xuantie RISC-V CPU☆42Jun 5, 2026Updated 3 months ago
- GCC for Xuantie RISC-V CPU, the GNU Compiler Collection.☆21Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- IC design and development should be faster，simpler and more reliable☆2,020Dec 31, 2021Updated 4 years ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆105Feb 10, 2026Updated 7 months ago
- Patches & Script for AOSP to run on Xuantie RISC-V CPU☆482Aug 13, 2026Updated last month
- FuseSoC-based SoC for VeeR EH1 and EL2☆343Dec 11, 2024Updated last year
- The Ultra-Low Power RISC-V Core☆1,920Aug 6, 2025Updated last year
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,123Updated this week
- ☆2,263Updated this week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆952Aug 18, 2026Updated last month
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆163Oct 31, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Open-source high-performance RISC-V processor☆7,268Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆547Aug 19, 2026Updated last month
- Rocket Chip Generator☆3,869Sep 13, 2026Updated last week
- VeeR EH1 core☆968Jul 16, 2026Updated 2 months ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,241Sep 11, 2026Updated last week
- OpenBouffalo Firmware Repository☆40Jul 25, 2023Updated 3 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆281Nov 6, 2024Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆638Sep 14, 2026Updated last week
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆116Apr 12, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RISC-V Open Source Supervisor Binary Interface☆1,531Updated this week
- Mainline-friendly SPL for D1☆37Nov 1, 2022Updated 3 years ago
- VeeR EH2 core☆280Updated this week
- PCB libraries and templates for rocket-chip based FPGA/ASIC designs☆19Jun 4, 2026Updated 3 months ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,063Updated this week
- Simple RISC-V 3-stage Pipeline in Chisel☆619Aug 9, 2024Updated 2 years ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆230Jan 11, 2026Updated 8 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,291Aug 26, 2026Updated 3 weeks ago
- RISC-V Debug Specification Standard☆529Aug 26, 2026Updated 3 weeks ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Functional verification project for the CORE-V family of RISC-V cores.☆723Updated this week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆261Aug 18, 2026Updated last month
- 3-stage RV32IMACZb* processor with debug☆1,110Aug 29, 2026Updated 3 weeks ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,384Sep 7, 2026Updated 2 weeks ago
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆31Feb 10, 2026Updated 7 months ago
- VeeR EL2 Core☆344Updated this week
- Nuclei AI Library Optimized For RISC-V Vector☆16Oct 15, 2025Updated 11 months ago