OpenXuantie - OpenC906 Core
☆393Jun 28, 2024Updated last year
Alternatives and similar repositories for openc906
Users that are interested in openc906 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- OpenXuantie - OpenC910 Core☆1,397Jun 28, 2024Updated last year
- OpenXuantie - OpenE902 Core☆172Jun 28, 2024Updated last year
- OpenXuantie - OpenE906 Core☆153Jun 28, 2024Updated last year
- Yocto project for Xuantie RISC-V CPU☆41Aug 8, 2025Updated 7 months ago
- IC design and development should be faster，simpler and more reliable☆1,986Dec 31, 2021Updated 4 years ago
- An optimized neural network operator library for chips base on Xuantie CPU.☆99Feb 10, 2026Updated last month
- Patches & Script for AOSP to run on Xuantie RISC-V CPU☆475Jun 18, 2024Updated last year
- FuseSoC-based SoC for VeeR EH1 and EL2☆338Dec 11, 2024Updated last year
- The Ultra-Low Power RISC-V Core☆1,774Aug 6, 2025Updated 7 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,851Updated this week
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆878Mar 16, 2026Updated last week
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆108Apr 12, 2025Updated 11 months ago
- ☆1,939Updated this week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆156Oct 31, 2024Updated last year
- Nuclei AI Library Optimized For RISC-V Vector☆14Oct 15, 2025Updated 5 months ago
- VeeR EH1 core☆931May 29, 2023Updated 2 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆500Mar 14, 2026Updated last week
- Rocket Chip Generator☆3,722Feb 25, 2026Updated 3 weeks ago
- OpenBouffalo Firmware Repository☆39Jul 25, 2023Updated 2 years ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆261Nov 6, 2024Updated last year
- Mainline-friendly SPL for D1☆34Nov 1, 2022Updated 3 years ago
- RISC-V Open Source Supervisor Binary Interface☆1,414Updated this week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,111Mar 11, 2026Updated last week
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,804Feb 17, 2026Updated last month
- Simple RISC-V 3-stage Pipeline in Chisel☆604Aug 9, 2024Updated last year
- ☆261Dec 22, 2022Updated 3 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆577Mar 11, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,197May 26, 2025Updated 9 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆224Jan 11, 2026Updated 2 months ago
- Working Draft of the RISC-V Debug Specification Standard☆507Mar 14, 2026Updated last week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,024Jun 27, 2024Updated last year
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆31Feb 10, 2026Updated last month
- 3-stage RV32IMACZb* processor with debug☆1,015Mar 14, 2026Updated last week
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- Open-source high-performance RISC-V processor☆6,904Updated this week
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,157Feb 21, 2026Updated last month
- ☆94Sep 30, 2025Updated 5 months ago
- riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)☆87Jan 21, 2022Updated 4 years ago
- RISC-V Cores, SoC platforms and SoCs☆918Mar 26, 2021Updated 4 years ago