samehattia / StateMover
StateMover is a checkpoint-based debugging framework for FPGAs.
☆19Updated 2 years ago
Alternatives and similar repositories for StateMover:
Users that are interested in StateMover are comparing it to the libraries listed below
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆56Updated 2 weeks ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆59Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 2 months ago
- ☆41Updated 6 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- Advanced Architecture Labs with CVA6☆54Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆66Updated this week
- ☆25Updated last year
- ☆32Updated 3 weeks ago
- PCI Express controller model☆49Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 4 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆30Updated last week
- ☆22Updated last year
- HLS for Networks-on-Chip☆33Updated 4 years ago
- Platform Level Interrupt Controller☆36Updated 10 months ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆24Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 5 months ago
- ☆27Updated 3 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆21Updated 6 years ago
- Simple single-port AXI memory interface☆38Updated 9 months ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- ☆18Updated this week
- ☆23Updated 2 weeks ago
- Pure digital components of a UCIe controller☆55Updated last week