xbwpc / EDA_FeatureColleLinks
A collection of license features from a varity of EDA vendors
☆74Updated 2 weeks ago
Alternatives and similar repositories for EDA_FeatureColle
Users that are interested in EDA_FeatureColle are comparing it to the libraries listed below
Sorting:
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆183Updated 2 months ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆103Updated last year
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- Synopsys License patcher☆36Updated 11 months ago
- AXI DMA 32 / 64 bits☆120Updated 11 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆139Updated last year
- ☆65Updated 5 years ago
- Some useful documents of Synopsys☆82Updated 3 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆69Updated 5 years ago
- This is the repository for the IEEE version of the book☆71Updated 4 years ago
- AHB3-Lite Interconnect☆90Updated last year
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- amba3 apb/axi vip☆51Updated 10 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Yet Another Simulation Architecture☆73Updated 4 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆217Updated 2 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆147Updated 7 years ago
- ☆68Updated 9 years ago
- [WIP] Dockerize Synopsys/Cadence EDA tools☆90Updated 6 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Novel GUI Based UVM Testbench Template Builder☆141Updated 4 years ago
- AXI总线连接器☆103Updated 5 years ago
- UVM Generator☆47Updated last year
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- An AXI4 crossbar implementation in SystemVerilog☆173Updated this week
- This is the main repository for all the examples for the book Practical UVM☆201Updated 4 years ago
- ☆143Updated 4 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆79Updated last year