A collection of license features from a varity of EDA vendors
☆85Aug 14, 2025Updated 6 months ago
Alternatives and similar repositories for EDA_FeatureColle
Users that are interested in EDA_FeatureColle are comparing it to the libraries listed below
Sorting:
- Synopsys License patcher☆39Sep 12, 2024Updated last year
- licenseMonitor is used to check instant EDA license information.☆28Aug 11, 2025Updated 6 months ago
- Patch cadence products☆58Jan 17, 2024Updated 2 years ago
- There is segmentation fault of VCS which should be fixed.☆42Sep 19, 2023Updated 2 years ago
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆196Jan 28, 2026Updated last month
- UVM/systemverilog/verilog/python VIM IDE☆16Aug 21, 2013Updated 12 years ago
- Siemens/Mentor EDA software license generate and patch tool☆47May 2, 2023Updated 2 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆20Dec 15, 2020Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Jan 31, 2020Updated 6 years ago
- Basic Simulink Blocks for modeling CDRs and PLLs☆15Apr 25, 2020Updated 5 years ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆11Apr 19, 2022Updated 3 years ago
- Simulink model for noise shaping SAR ADC☆12Mar 17, 2020Updated 5 years ago
- A verilog FPGA Interface for AXI4_Lite from Slave side☆11Jun 14, 2020Updated 5 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC☆41Jun 13, 2023Updated 2 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆237Jul 16, 2023Updated 2 years ago
- ☆12Jan 19, 2022Updated 4 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 5 years ago
- Edit SystemVerilog files (and UVM files) in Vim/gVim☆30Mar 8, 2024Updated last year
- syn script for DC Compiler☆14May 15, 2022Updated 3 years ago
- ☆15Apr 30, 2021Updated 4 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆26Mar 13, 2025Updated 11 months ago
- Testbenches for HDL projects☆22Updated this week
- Verification IP project for I3C protocol☆24Feb 13, 2026Updated 2 weeks ago
- DOULOS Easier UVM Code Generator☆39May 6, 2017Updated 8 years ago
- IEEE P1735 decryptor for VHDL☆39Jun 23, 2015Updated 10 years ago
- ☆19Oct 29, 2025Updated 4 months ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- Python package for working with Keysight/Agilent/HP test equipment.☆18Dec 5, 2024Updated last year
- Mirror of tachyon-da cvc Verilog simulator☆48Jul 16, 2023Updated 2 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Dec 8, 2012Updated 13 years ago
- Completed LDO Design for Skywaters 130nm☆19Feb 16, 2023Updated 3 years ago
- VerMFi: Verification tool for Masked implementations and Fault injection. Set of tools to evaluate resistance of secure hardware against …☆20Nov 18, 2019Updated 6 years ago
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆23Jun 26, 2023Updated 2 years ago
- A MCU implementation based PODES-M0O☆19Jan 31, 2020Updated 6 years ago
- draw interface wave by python☆19Jan 11, 2025Updated last year
- A toop for openlava data-collection, data-analysis and information display.☆19Jul 17, 2024Updated last year
- Verification IP for UART protocol☆23Aug 3, 2020Updated 5 years ago
- Quad cluster of RISC-V cores with peripherals and local memory☆24Feb 3, 2022Updated 4 years ago