xbwpc / EDA_FeatureColleLinks
A collection of license features from a varity of EDA vendors
☆74Updated last month
Alternatives and similar repositories for EDA_FeatureColle
Users that are interested in EDA_FeatureColle are comparing it to the libraries listed below
Sorting:
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆104Updated last year
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- Synopsys License patcher☆36Updated last year
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆70Updated 5 years ago
- This is the repository for the IEEE version of the book☆71Updated 4 years ago
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆184Updated 3 months ago
- Some useful documents of Synopsys☆85Updated 3 years ago
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- AHB3-Lite Interconnect☆93Updated last year
- Yet Another Simulation Architecture☆75Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆80Updated last year
- amba3 apb/axi vip☆51Updated 10 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Novel GUI Based UVM Testbench Template Builder☆141Updated 4 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆148Updated 7 years ago
- ☆69Updated 9 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆139Updated last year
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- This is for uvm_tb_gen☆39Updated 7 months ago
- There is segmentation fault of VCS which should be fixed.☆38Updated 2 years ago
- This is the main repository for all the examples for the book Practical UVM☆202Updated 4 years ago
- ☆65Updated 5 years ago
- UVM Generator☆47Updated last year
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- [WIP] Dockerize Synopsys/Cadence EDA tools☆90Updated 6 years ago
- ☆73Updated 4 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆222Updated 2 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆64Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆175Updated 3 weeks ago
- UVM实战随书源码☆54Updated 6 years ago