Open IP in Hardware Description Language.
☆32Sep 4, 2023Updated 2 years ago
Alternatives and similar repositories for openip-hdl
Users that are interested in openip-hdl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A harvard architecture CPU based on RISC-V.☆16Aug 25, 2023Updated 2 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆27Updated this week
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated last year
- A project demonstrate how to config ad9361 to TX mode☆11Dec 9, 2018Updated 7 years ago
- RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer…☆28Jul 12, 2024Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆43Oct 7, 2023Updated 2 years ago
- ☆48Jan 6, 2026Updated 4 months ago
- Residual vector quantization for KV cache compression in large language model☆12Oct 22, 2024Updated last year
- My code repositry for common use.☆23Dec 31, 2021Updated 4 years ago
- ☆40May 13, 2026Updated last week
- ☆63Feb 18, 2019Updated 7 years ago
- Extremely Simple Microbenchmarks☆44May 23, 2018Updated 7 years ago
- HYF's high quality verilog codes☆18Dec 25, 2024Updated last year
- AIChip 2021 project, NCKU☆18May 6, 2021Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Fractional interpolation using a Farrow structure☆10Oct 11, 2023Updated 2 years ago
- Turbo coder and decoder☆12Oct 11, 2023Updated 2 years ago
- FPGA/hardware design of openwifi☆18Nov 28, 2025Updated 5 months ago
- 16QAM modulation and demodulation by Verilog☆21Jan 4, 2021Updated 5 years ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- GMSK调制和解调matlab代码☆17Apr 22, 2023Updated 3 years ago
- ☆18Mar 31, 2026Updated last month
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- ☆10Mar 26, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆76Aug 13, 2024Updated last year
- ☆10Apr 20, 2026Updated last month
- APB Logic☆26Updated this week
- ☆31Jan 23, 2021Updated 5 years ago
- synthesiseable ieee 754 floating point library in verilog☆739Mar 13, 2023Updated 3 years ago
- Tiny Tapeout GDS Action (using LibreLane)☆22Apr 26, 2026Updated 3 weeks ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- C++ implementation of inference of mobilenet☆17May 1, 2020Updated 6 years ago
- OFDM baseband processing systerm based on IEEE 802.11a☆13Aug 3, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆12Jul 29, 2016Updated 9 years ago
- Official code base of the BEVDet series .☆11Oct 9, 2022Updated 3 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…☆327Sep 14, 2023Updated 2 years ago
- OpenXuantie - OpenE906 Core☆166Jun 28, 2024Updated last year
- EECS 151/251A FPGA Project Skeleton for Spring 2020☆12May 6, 2020Updated 6 years ago
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆28Dec 18, 2024Updated last year
- Attentionlego☆13Jan 24, 2024Updated 2 years ago