Open IP in Hardware Description Language.
☆29Sep 4, 2023Updated 2 years ago
Alternatives and similar repositories for openip-hdl
Users that are interested in openip-hdl are comparing it to the libraries listed below
Sorting:
- A harvard architecture CPU based on RISC-V.☆15Aug 25, 2023Updated 2 years ago
- A project demonstrate how to config ad9361 to TX mode☆11Dec 9, 2018Updated 7 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆26Sep 9, 2025Updated 5 months ago
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated last year
- RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer…☆27Jul 12, 2024Updated last year
- APB Logic☆24Updated this week
- My code repositry for common use.☆23Dec 31, 2021Updated 4 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- ☆58Feb 18, 2019Updated 7 years ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆26Apr 29, 2021Updated 4 years ago
- ☆24Apr 18, 2021Updated 4 years ago
- ☆32Jan 23, 2021Updated 5 years ago
- Hardware Assisted IEEE 1588 IP Core☆30Jul 17, 2014Updated 11 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆31Feb 10, 2020Updated 6 years ago
- An AXI DDR3 SDRAM controller for FPGA☆44Dec 30, 2023Updated 2 years ago
- Fractional interpolation using a Farrow structure☆10Oct 11, 2023Updated 2 years ago
- GMSK调制和解调matlab代码☆15Apr 22, 2023Updated 2 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- Modular Multi-ported SRAM-based Memory☆31Nov 8, 2024Updated last year
- 哈工大软件无线电课设：多相滤波器的原理、实现及其应用，从采样率变换、多相滤波器结构到信道化收发机应用都有matlab介绍和FPGA仿真结果，含答辩PPT、学习笔记和个人总结。☆96Apr 19, 2017Updated 8 years ago
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 3 years ago
- ☆36Jun 19, 2023Updated 2 years ago
- 用Verilog语言编写，实现2FSK，2PSK, 2DPSK, QPSK调制解调☆43Mar 15, 2019Updated 6 years ago
- ☆10Oct 18, 2024Updated last year
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- 2019年全国大学生电子设计大赛G题双路语音调频接收机的FPGA全实现☆17Apr 15, 2020Updated 5 years ago
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- Extremely Simple Microbenchmarks☆41May 23, 2018Updated 7 years ago
- Design of High-Level Synthesis of Xilinx FFT IP core via FFT library☆13Jul 17, 2023Updated 2 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- mechatronics firmware☆13Apr 14, 2025Updated 10 months ago
- Fast Sparse Multifrontal Solver☆11May 27, 2015Updated 10 years ago
- ☆14Jan 22, 2026Updated last month
- VHDL sources for a BT.656 to axi4-stream converter☆12Mar 20, 2023Updated 2 years ago
- Turbo coder and decoder☆12Oct 11, 2023Updated 2 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- Code repository for my articles on blogs.embarcadero.com and pythongui.org.☆13Feb 6, 2025Updated last year