Alternatives and similar repositories for qemu

Users that are interested in qemu are comparing it to the libraries listed below

• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆72Updated last year
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆46Updated 11 months ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆43Updated last month
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆56Updated 4 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆138Updated 3 years ago
• riscv / riscv-aia
  ☆98Updated last week
• riscvarchive / riscv-CMOs
  ☆89Updated 4 months ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• mollybuild / RISCV-Measurement
  This is a repo for recording and reporting RISCV platform's test and measurement continuously.
  ☆59Updated 2 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆145Updated 2 weeks ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated last week
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆94Updated 7 months ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆105Updated 7 years ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆150Updated 4 months ago
• cnrv / RISCV-East-Asia-Biweekly-Sync
  Biweekly Sync Meeting for RISC-V Software Ecosystem. Meeting time is more friendly for people living in East Asia.
  ☆23Updated last month
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆76Updated last month
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆190Updated 2 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆98Updated last month
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆166Updated this week
• XUANTIE-RV / xuantie-gnu-toolchain
  GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……
  ☆106Updated 8 months ago
• OpenXiangShan / GEM5
  ☆120Updated this week
• OSCPU / chisel-playground
  ☆68Updated 10 months ago
• cnrv / RVSC2023
  RISC-V Summit China 2023
  ☆40Updated 2 years ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆33Updated 2 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆107Updated 3 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆16Updated last year
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆159Updated 7 months ago