Qemu for Xuantie RISC-V CPU, a generic machine emulator and virtualizer.
☆51Jul 30, 2025Updated 7 months ago
Alternatives and similar repositories for qemu
Users that are interested in qemu are comparing it to the libraries listed below
Sorting:
- ☆17Feb 11, 2026Updated 2 weeks ago
- GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……☆108Apr 12, 2025Updated 10 months ago
- RTOS based on L4 microkernel.☆17Sep 18, 2018Updated 7 years ago
- ☆12Jan 18, 2018Updated 8 years ago
- Header-only C/C++ static keys to avoid the overhead of conditional branches☆14Feb 10, 2024Updated 2 years ago
- Logical Table Based Switch Software Development Kit☆15Jul 13, 2022Updated 3 years ago
- ☆12Jun 27, 2022Updated 3 years ago
- A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.☆14Aug 7, 2022Updated 3 years ago
- PLCT实验室维护的QEMU仓库。代码放在 plct- 前缀的分支里。☆30Sep 18, 2025Updated 5 months ago
- ☆15Dec 15, 2022Updated 3 years ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆13Dec 4, 2025Updated 2 months ago
- GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk☆16Jun 3, 2021Updated 4 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- 第六届龙芯杯混元形意太极门战队作品☆18May 15, 2022Updated 3 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Apr 7, 2025Updated 10 months ago
- "High density" digital standard cells for SKY130 provided by SkyWater.☆23Feb 22, 2023Updated 3 years ago
- Linux kernel source tree☆46Feb 13, 2025Updated last year
- Buildroot customized for Xuantie™ RISC-V CPU☆47Jan 17, 2022Updated 4 years ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆24Jan 11, 2026Updated last month
- ☆17Mar 17, 2022Updated 3 years ago
- 《计算机设计与实践》测试框架☆17Jun 28, 2022Updated 3 years ago
- My RV64 CPU (Work in progress)☆19Dec 22, 2022Updated 3 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆26Aug 16, 2023Updated 2 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last week
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Nov 26, 2025Updated 3 months ago
- Yocto project for Xuantie RISC-V CPU☆40Aug 8, 2025Updated 6 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Nov 24, 2025Updated 3 months ago
- "aura" my super-scalar O3 cpu core☆25May 25, 2024Updated last year
- ☆28Mar 13, 2020Updated 5 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆36Jan 26, 2026Updated last month
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated 4 months ago
- ☆32Feb 6, 2026Updated 3 weeks ago
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆30Feb 10, 2026Updated 3 weeks ago
- ☆66Aug 5, 2024Updated last year
- A Symmetric Multiprocessing OS Kernel over RISC-V☆32Jun 3, 2022Updated 3 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- ☆12Aug 12, 2022Updated 3 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆28Jun 25, 2025Updated 8 months ago
- ARINC653 Multi-Partition Operating System Based On RISC-V, capable of running on SiFive HiFive Unmatched.☆28Jun 25, 2023Updated 2 years ago