Alternatives and similar repositories for qemu

Users that are interested in qemu are comparing it to the libraries listed below

• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆45Updated 9 months ago
• riscv / riscv-aia
  ☆96Updated 2 months ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• XUANTIE-RV / xuantie-gnu-toolchain
  GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……
  ☆102Updated 6 months ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆149Updated 2 months ago
• riscvarchive / riscv-CMOs
  ☆89Updated 2 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆137Updated this week
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆106Updated 7 years ago
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆42Updated last year
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 3 years ago
• zetalog / sdfirm
  Ultra light weight small device firmware. Well architected to support MMU, SMP, low power idle. Can be run on various CPU architectures.
  ☆20Updated 2 months ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated last month
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆104Updated last month
• OpenXiangShan / GEM5
  ☆106Updated this week
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆154Updated 5 months ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆55Updated 4 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆16Updated last year
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆159Updated last week
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• mollybuild / RISCV-Measurement
  This is a repo for recording and reporting RISCV platform's test and measurement continuously.
  ☆59Updated last year
• chipsalliance / tilelink
  ☆35Updated 10 months ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 7 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆75Updated last week
• ucb-ucie / ucieanalog
  An open-source UCIe implementation developed at UC Berkeley.
  ☆17Updated last year
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆92Updated last month
• OSCPU / chisel-playground
  ☆67Updated 8 months ago