Alternatives and similar repositories for SpinalTemplateSbt:

Users that are interested in SpinalTemplateSbt are comparing it to the libraries listed below

• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆146Updated 6 months ago
• SpinalHDL / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆44Updated 9 months ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆57Updated last year
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆129Updated 7 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆61Updated 3 weeks ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆63Updated 5 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆61Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆82Updated 5 years ago
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆70Updated 10 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆82Updated 4 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆204Updated 4 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆101Updated 2 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆164Updated 2 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆157Updated 2 months ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated last year
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆93Updated 3 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆50Updated this week
• leros-dev / leros
  A Tiny Processor Core
  ☆104Updated 2 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆43Updated 2 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆99Updated 3 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆102Updated 3 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆182Updated last month
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆130Updated last month
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆130Updated last month
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆123Updated this week
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 8 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆108Updated 5 years ago