A basic SpinalHDL project
☆101Aug 15, 2025Updated last year
Alternatives and similar repositories for SpinalTemplateSbt
Users that are interested in SpinalTemplateSbt are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Labs to learn SpinalHDL☆159Jul 4, 2024Updated 2 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆49Apr 9, 2024Updated 2 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆153Jun 14, 2024Updated 2 years ago
- The sources of the online SpinalHDL doc☆32Oct 20, 2026Updated last week
- Scala based HDL☆2,053Oct 22, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- SpinalHDL documentation assets (pictures, slides, ...)☆32Dec 10, 2024Updated last year
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆56Jun 11, 2023Updated 3 years ago
- List of SpinalHDL projects, libraries, and learning resources.☆30Jan 6, 2026Updated 9 months ago
- ☆31Dec 15, 2021Updated 4 years ago
- SpinalHDL - Cryptography libraries☆62Jul 19, 2024Updated 2 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,301Oct 13, 2026Updated 2 weeks ago
- SoC based on VexRiscv and ICE40 UP5K☆166Mar 16, 2025Updated last year
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆70Jan 8, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆328Jan 23, 2026Updated 9 months ago
- Demo Sources for Learning Spinal HDL☆17Dec 5, 2022Updated 3 years ago
- ☆24Feb 15, 2023Updated 3 years ago
- A version of f32c/arduino that works with the SpinalHDL Vexriscv Murax SoC☆15May 23, 2019Updated 7 years ago
- CNN accelerator implemented with Spinal HDL☆162Sep 29, 2026Updated last month
- Network components (NIC, Switch) for FireBox☆20Oct 27, 2024Updated 2 years ago
- CPOL=0, CPHA=0 SPI core for practicing formal verification with yosys☆21May 20, 2020Updated 6 years ago
- An open-source RTL NVMe controller IP for Xilinx FPGA.☆64Feb 25, 2021Updated 5 years ago
- SpinalHDL Hardware Math Library☆106Jul 12, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Provides various testers for chisel users☆101Jan 12, 2023Updated 3 years ago
- Using VexRiscv without installing Scala☆40Nov 10, 2021Updated 4 years ago
- understanding of cocotb (In Chinese Only)☆22Jun 10, 2025Updated last year
- This is my first trial project for designing RISC-V in Chisel☆17Apr 29, 2024Updated 2 years ago
- Wrapper for ETH Ariane Core☆21Sep 2, 2025Updated last year
- ☆13Feb 13, 2021Updated 5 years ago
- A 32-bit 5-stage RISC-V pipeline processor core with traps, S privilege mode, virtual memory, cache, branch prediction and TLB. Powered b…☆15Feb 14, 2024Updated 2 years ago
- A tool for those who want to use Vivado's batch mode more easily☆17Dec 16, 2019Updated 6 years ago
- A template project for beginning new Chisel work☆710Feb 24, 2026Updated 8 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 实现带有BD(Buffer Description缓存描述符)的四通道DMA控制器设计,每个通道包括配置寄存器模块,源端控制模 块,缓存模块和目的端控制模块☆12Sep 12, 2023Updated 3 years ago
- ☆90Jun 27, 2022Updated 4 years ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆27Aug 8, 2026Updated 2 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆267Updated this week
- CNN on Artix-7 FPGA to perform pattern detection from a pool of objects☆12Sep 12, 2018Updated 8 years ago
- Chisel NVMe controller☆29Nov 24, 2022Updated 3 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆38Mar 14, 2021Updated 5 years ago