SpinalHDL / SpinalTemplateSbt
A basic SpinalHDL project
☆81Updated 2 months ago
Alternatives and similar repositories for SpinalTemplateSbt:
Users that are interested in SpinalTemplateSbt are comparing it to the libraries listed below
- Labs to learn SpinalHDL☆146Updated 7 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- SpinalHDL-tutorial based on Jupyter Notebook☆44Updated 10 months ago
- SpinalHDL-tutorial based on Jupyter Notebook☆130Updated 8 months ago
- A Tiny Processor Core☆106Updated 3 months ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated last week
- SDRAM controller with AXI4 interface☆87Updated 5 years ago
- Chisel Learning Journey☆108Updated last year
- (System)Verilog to Chisel translator☆111Updated 2 years ago
- Provides various testers for chisel users☆101Updated 2 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- Network on Chip Implementation written in SytemVerilog☆167Updated 2 years ago
- Lipsi: Probably the Smallest Processor in the World☆82Updated 10 months ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 3 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- Chisel components for FPGA projects☆120Updated last year
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 2 months ago
- ☆53Updated 4 years ago
- AHB3-Lite Interconnect☆83Updated 9 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆160Updated 3 months ago
- An AXI4 crossbar implementation in SystemVerilog☆131Updated 2 months ago
- Platform Level Interrupt Controller☆36Updated 9 months ago
- ☆77Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆49Updated 5 years ago
- Vector processor for RISC-V vector ISA☆113Updated 4 years ago
- round robin arbiter☆70Updated 10 years ago