abmfy / cod23-grp04
A 32-bit 5-stage RISC-V pipeline processor core with traps, S privilege mode, virtual memory, cache, branch prediction and TLB. Powered by SpinalHDL and Verilator. Supports running simple OS like uCore. Course project of Computer Organization and Design, Tsinghua University.
☆13Updated 9 months ago
Related projects ⓘ
Alternatives and complementary repositories for cod23-grp04
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆69Updated last year
- ☆31Updated last year
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆37Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆25Updated 7 months ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…☆35Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆24Updated 6 months ago
- 2022龙芯杯个人赛三等奖作品☆13Updated last year
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 8 months ago
- ☆56Updated 4 months ago
- ☆60Updated 3 months ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆45Updated 11 months ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆24Updated 4 months ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆40Updated 4 years ago
- ☆10Updated 3 months ago
- ☆43Updated 4 months ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆22Updated 8 months ago
- NSCSCC 2020 - Yet Another MIPS Processor☆14Updated 3 years ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆16Updated 4 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆43Updated 3 weeks ago
- ☆76Updated 2 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆116Updated last month
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆13Updated last month
- ☆11Updated 5 months ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆8Updated 7 months ago
- 2022年龙芯杯个人赛 单发射110M（含icache）☆43Updated 2 years ago
- Modern co-simulation framework for RISC-V CPUs☆118Updated this week
- Pick your favorite language to verify your chip.☆31Updated this week
- CQU Dual Issue Machine☆34Updated 5 months ago
- ☆20Updated last year