abmfy / cod23-grp04
A 32-bit 5-stage RISC-V pipeline processor core with traps, S privilege mode, virtual memory, cache, branch prediction and TLB. Powered by SpinalHDL and Verilator. Supports running simple OS like uCore. Course project of Computer Organization and Design, Tsinghua University.
☆11Updated 7 months ago
Related projects: ⓘ
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆65Updated last year
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆34Updated last year
- ☆32Updated last year
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆33Updated 2 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆25Updated 5 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆18Updated 6 months ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆44Updated 9 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆43Updated 2 months ago
- ☆40Updated 2 months ago
- "aura" my super-scalar O3 cpu core☆24Updated 3 months ago
- 2022龙芯杯个人赛三等奖作品☆13Updated 11 months ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆15Updated 2 months ago
- NSCSCC 2020 - Yet Another MIPS Processor☆14Updated 3 years ago
- ☆54Updated 2 months ago
- Introduction to Computer Systems (II), Spring 2021☆46Updated 3 years ago
- ☆55Updated last month
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆41Updated 4 years ago
- ☆21Updated last month
- 适用于龙芯杯团队赛入门选手的应急cache模块☆21Updated 6 months ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆22Updated last month
- ☆10Updated last month
- 清华大学《计算机组成原理》大实验——五级流水线 RISC-V 处理器。「奋战三星期,造台计算机」☆12Updated last year
- ☆75Updated last week
- CQU Dual Issue Machine☆31Updated 2 months ago
- A classic five stage pipelined processor☆13Updated 6 months ago
- ☆18Updated 9 months ago
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆34Updated 4 years ago
- Documentation for Digital Design course☆19Updated 2 months ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆120Updated 2 months ago
- Online judge server for Verilog | verilogoj.ustc.edu.cn☆75Updated 2 months ago