agra-uni-bremen / microrv32Links
SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
☆51Updated last year
Alternatives and similar repositories for microrv32
Users that are interested in microrv32 are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 4 months ago
- RISC-V Nox core☆69Updated 4 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- For contributions of Chisel IP to the chisel community.☆68Updated last year
- SpinalHDL Hardware Math Library☆93Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆102Updated this week
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆70Updated last week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- Platform Level Interrupt Controller☆44Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last week
- A simple DDR3 memory controller☆61Updated 2 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆98Updated 5 months ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆52Updated 3 weeks ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- ☆60Updated 4 years ago
- ☆33Updated last month
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- An implementation of RISC-V☆44Updated 2 months ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆126Updated 6 months ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- RISC-V System on Chip Template☆159Updated 3 months ago