SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
☆56Feb 2, 2026Updated 9 months ago
Alternatives and similar repositories for microrv32
Users that are interested in microrv32 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A reimplementation of a tiny stack CPU☆90Dec 8, 2023Updated 2 years ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Oct 4, 2023Updated 3 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆64Oct 30, 2026Updated last week
- ☆328Jan 23, 2026Updated 9 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆70Jan 8, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆268Oct 31, 2026Updated last week
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 6 months ago
- Virtual Breadboard / PCB simulation for Prototyping and Educational Purposes☆16Jun 4, 2023Updated 3 years ago
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 7 years ago
- The hardware implementation of Poseidon hash function in SpinalHDL☆21Jun 5, 2022Updated 4 years ago
- RISC-V Virtual Prototype☆196Jul 21, 2026Updated 3 months ago
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 6 years ago
- A RISC-V VP with SUBLEQ microcode☆13Sep 29, 2022Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆38Mar 14, 2021Updated 5 years ago
- SpinalHDL Hardware Math Library☆106Jul 12, 2024Updated 2 years ago
- MR1 formally verified RISC-V CPU☆60Dec 16, 2018Updated 7 years ago
- Labs to learn SpinalHDL☆159Jul 4, 2024Updated 2 years ago
- benchmarks for hls equivalence checking☆11Nov 22, 2022Updated 3 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- RISCV lock-step checker based on Spike☆16Sep 20, 2026Updated last month
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- Scala based HDL☆2,057Oct 30, 2026Updated last week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- SpinalHDL-tutorial based on Jupyter Notebook☆153Jun 14, 2024Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆61Oct 19, 2026Updated 2 weeks ago
- List of SpinalHDL projects, libraries, and learning resources.☆30Jan 6, 2026Updated 10 months ago
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 3 years ago
- ☆15Dec 6, 2023Updated 2 years ago
- Naive Educational RISC V processor☆103Oct 12, 2025Updated last year
- RISC-V processor☆32May 26, 2022Updated 4 years ago
- CoralNPU behavior simulator based on MPACT-Sim☆29Oct 8, 2026Updated last month
- CNN accelerator implemented with Spinal HDL☆162Sep 29, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆41Feb 6, 2024Updated 2 years ago
- Writing my own Verilog code for the book <Advanced Chip Design Practical Examples in Verilog>☆10May 4, 2023Updated 3 years ago
- Virtual Prototype for identifying Application Specific Hardware Optimization candidates☆12Oct 27, 2026Updated last week
- betrusted.io main SoC design☆15Jan 30, 2020Updated 6 years ago
- Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture☆15Jul 24, 2020Updated 6 years ago
- The code for an FPGA softcore comparison☆11Jun 21, 2020Updated 6 years ago
- Tools for manipulating CHC and related files☆15Apr 21, 2023Updated 3 years ago