SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
☆56Feb 2, 2026Updated 8 months ago
Alternatives and similar repositories for microrv32
Users that are interested in microrv32 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A reimplementation of a tiny stack CPU☆90Dec 8, 2023Updated 2 years ago
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Oct 4, 2023Updated 3 years ago
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated 2 years ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- The hardware implementation of Poseidon hash function in SpinalHDL☆21Jun 5, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 5 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆70Jan 8, 2024Updated 2 years ago
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 7 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆262Oct 9, 2026Updated last week
- A RISC-V VP with SUBLEQ microcode☆13Sep 29, 2022Updated 4 years ago
- ☆328Jan 23, 2026Updated 8 months ago
- MR1 formally verified RISC-V CPU☆60Dec 16, 2018Updated 7 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆64Sep 28, 2026Updated 2 weeks ago
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 3 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- RISC-V Virtual Prototype☆195Jul 21, 2026Updated 2 months ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 6 years ago
- RISCV lock-step checker based on Spike☆16Sep 20, 2026Updated 3 weeks ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆38Mar 14, 2021Updated 5 years ago
- RISC-V processor☆32May 26, 2022Updated 4 years ago
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆61Oct 8, 2026Updated last week
- ☆15Dec 6, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- List of SpinalHDL projects, libraries, and learning resources.☆30Jan 6, 2026Updated 9 months ago
- Scala based HDL☆2,053Oct 6, 2026Updated last week
- Labs to learn SpinalHDL☆159Jul 4, 2024Updated 2 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆153Jun 14, 2024Updated 2 years ago
- The code for an FPGA softcore comparison☆11Jun 21, 2020Updated 6 years ago
- Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture☆15Jul 24, 2020Updated 6 years ago
- A Hardware Implemented Poseidon Hasher☆21Apr 15, 2022Updated 4 years ago
- SpinalHDL Hardware Math Library☆105Jul 12, 2024Updated 2 years ago
- Naive Educational RISC V processor☆102Oct 12, 2025Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- ☆19Dec 21, 2020Updated 5 years ago
- [FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic M…☆23May 6, 2024Updated 2 years ago
- SpinalHDL - Cryptography libraries☆62Jul 19, 2024Updated 2 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆11Dec 29, 2021Updated 4 years ago
- DUTH RISC V Microprocessor for High Level Synthesis☆10Jun 23, 2023Updated 3 years ago
- CNN accelerator implemented with Spinal HDL☆162Sep 29, 2026Updated 2 weeks ago
- ☆13Sep 18, 2026Updated last month