agra-uni-bremen / microrv32Links
SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
☆53Updated this week
Alternatives and similar repositories for microrv32
Users that are interested in microrv32 are comparing it to the libraries listed below
Sorting:
- RISC-V Nox core☆71Updated 6 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- An implementation of RISC-V☆47Updated last month
- ☆60Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated 2 months ago
- Platform Level Interrupt Controller☆44Updated last year
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 4 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆80Updated 2 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Updated 4 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆56Updated this week
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 8 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 5 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- ☆34Updated last month
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆80Updated last year
- SpinalHDL Hardware Math Library☆94Updated last year
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- 64-bit multicore Linux-capable RISC-V processor☆105Updated 9 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated last month
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- ☆58Updated 10 months ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆100Updated 7 months ago