Alternatives and similar repositories for SpinalDoc-RTD

Users that are interested in SpinalDoc-RTD are comparing it to the libraries listed below

• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆62Updated last year
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 7 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆61Updated 7 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• jjyy-Huang / SpinalHDL-ethernet
  ☆18Updated 2 years ago
• SpinalHDL / CocotbLib
  ☆16Updated 2 years ago
• SpinalHDL / SpinalTemplateSbt
  A basic SpinalHDL project
  ☆86Updated 2 months ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆32Updated last year
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆60Updated 4 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆47Updated 7 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 10 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆69Updated this week
• verilator / example-systemverilog
  ☆38Updated last year
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆53Updated last year
• pulp-platform / axi_llc
  ☆29Updated last month
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆48Updated last year
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆32Updated 5 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 5 months ago
• SpinalHDL / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆45Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆55Updated this week
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆43Updated 4 months ago
• zao111222333 / spinalhdl-online
  ☆24Updated 2 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆38Updated 4 years ago
• pulp-platform / axi2apb
  ☆20Updated 5 years ago