The sources of the online SpinalHDL doc
☆30Mar 6, 2026Updated 2 weeks ago
Alternatives and similar repositories for SpinalDoc-RTD
Users that are interested in SpinalDoc-RTD are comparing it to the libraries listed below
Sorting:
- A basic SpinalHDL project☆91Aug 15, 2025Updated 7 months ago
- SpinalHDL documentation assets (pictures, slides, ...)☆32Dec 10, 2024Updated last year
- ☆22Feb 15, 2023Updated 3 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆152Jun 14, 2024Updated last year
- Labs to learn SpinalHDL☆155Jul 4, 2024Updated last year
- SpinalHDL - Cryptography libraries☆59Jul 19, 2024Updated last year
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 2 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, op…☆113Sep 17, 2022Updated 3 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Jul 30, 2021Updated 4 years ago
- Scala based HDL☆1,935Updated this week
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 7 years ago
- Docker Development Environment for SpinalHDL☆20Aug 8, 2024Updated last year
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆56Jun 11, 2023Updated 2 years ago
- Demo Sources for Learning Spinal HDL☆16Dec 5, 2022Updated 3 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆22Feb 4, 2025Updated last year
- Parsing library for BLIF netlists☆19Nov 1, 2024Updated last year
- SoC based on VexRiscv and ICE40 UP5K☆161Mar 16, 2025Updated last year
- SpinalHDL Hardware Math Library☆96Jul 12, 2024Updated last year
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 5 years ago
- List of SpinalHDL projects, libraries, and learning resources.☆25Jan 6, 2026Updated 2 months ago
- Signal Processing in Scala☆30Jan 15, 2014Updated 12 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Oct 9, 2021Updated 4 years ago
- Chisel Things for OFDM☆32Jul 1, 2020Updated 5 years ago
- ☆18Jul 9, 2025Updated 8 months ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 5 years ago
- ☆11Jul 12, 2023Updated 2 years ago
- riscv.github.io☆11Jul 27, 2020Updated 5 years ago
- Fractional interpolation using a Farrow structure☆10Oct 11, 2023Updated 2 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆206Updated this week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆63Dec 15, 2025Updated 3 months ago
- An FPGA in your USB Port☆11Jul 1, 2021Updated 4 years ago
- Digital signal processing library☆18Oct 13, 2020Updated 5 years ago
- Qemu for the EFM32HG (for Tomu development)☆13Jan 23, 2017Updated 9 years ago
- A programming language for FPGAs.☆20May 5, 2018Updated 7 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆20Apr 15, 2022Updated 3 years ago
- Uart module written in chisel☆13Feb 19, 2016Updated 10 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆47Mar 3, 2024Updated 2 years ago
- Text editor that mimicks the famous nano, written in go.☆15Dec 11, 2020Updated 5 years ago
- ☆309Jan 23, 2026Updated last month