Alternatives and similar repositories for SpinalDoc-RTD

Users that are interested in SpinalDoc-RTD are comparing it to the libraries listed below

• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆94Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆144Updated this week
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated 2 years ago
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆51Updated 6 months ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆49Updated last year
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated last week
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆32Updated last year
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆51Updated last year
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated last month
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated last year
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆57Updated 6 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 2 weeks ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆41Updated 8 years ago
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆153Updated last week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆43Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆19Updated 2 years ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 5 months ago
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆37Updated last year
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆43Updated 4 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆30Updated 3 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆32Updated last year
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆64Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆53Updated last month
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 7 months ago
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆28Updated this week
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆15Updated 8 years ago