SpinalHDL / SpinalDoc-RTDLinks
The sources of the online SpinalHDL doc
☆29Updated 3 weeks ago
Alternatives and similar repositories for SpinalDoc-RTD
Users that are interested in SpinalDoc-RTD are comparing it to the libraries listed below
Sorting:
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- A basic SpinalHDL project☆87Updated 3 months ago
- SpinalHDL Hardware Math Library☆88Updated last year
- SpinalHDL-tutorial based on Jupyter Notebook☆45Updated last year
- Sphinx Extension which generates various types of diagrams from Verilog code.☆61Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- Open FPGA Modules☆24Updated 9 months ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆64Updated 5 years ago
- SystemVerilog FSM generator☆32Updated last year
- Re-coded Xilinx primitives for Verilator use☆50Updated 3 weeks ago
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆57Updated last week
- A simple DDR3 memory controller☆57Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆37Updated 3 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆137Updated 3 weeks ago
- hardware library for hwt (= ipcore repo)☆40Updated this week
- Extensible FPGA control platform☆62Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- Simple parser for extracting VHDL documentation☆71Updated last year
- YosysHQ SVA AXI Properties☆41Updated 2 years ago
- Labs to learn SpinalHDL☆149Updated last year
- Open source process design kit for 28nm open process☆59Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆72Updated 10 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆62Updated last week
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆49Updated 8 months ago
- ☆19Updated 2 years ago