The sources of the online SpinalHDL doc
☆30Updated this week
Alternatives and similar repositories for SpinalDoc-RTD
Users that are interested in SpinalDoc-RTD are comparing it to the libraries listed below
Sorting:
- A basic SpinalHDL project☆90Aug 15, 2025Updated 6 months ago
- SpinalHDL documentation assets (pictures, slides, ...)☆32Dec 10, 2024Updated last year
- SpinalHDL - Cryptography libraries☆59Jul 19, 2024Updated last year
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆68Jan 8, 2024Updated 2 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Sep 17, 2022Updated 3 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆54Jun 11, 2023Updated 2 years ago
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 2 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆47Apr 9, 2024Updated last year
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 7 years ago
- Demo Sources for Learning Spinal HDL☆16Dec 5, 2022Updated 3 years ago
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 5 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Jul 30, 2021Updated 4 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆21Feb 4, 2025Updated last year
- ☆18Jul 9, 2025Updated 7 months ago
- Scala based HDL☆1,928Feb 18, 2026Updated last week
- Parsing library for BLIF netlists☆19Nov 1, 2024Updated last year
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 5 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆20Apr 15, 2022Updated 3 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 7 years ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Oct 22, 2024Updated last year
- List of SpinalHDL projects, libraries, and learning resources.☆25Jan 6, 2026Updated last month
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 2 years ago
- Re-coded Xilinx primitives for Verilator use☆51Jun 24, 2025Updated 8 months ago
- SpinalHDL Hardware Math Library☆96Jul 12, 2024Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆53Jan 31, 2026Updated last month
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Mar 11, 2023Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆63Dec 15, 2025Updated 2 months ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆110Oct 31, 2023Updated 2 years ago
- SoC based on VexRiscv and ICE40 UP5K☆161Mar 16, 2025Updated 11 months ago
- Chisel Things for OFDM☆32Jul 1, 2020Updated 5 years ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆34Jan 2, 2024Updated 2 years ago
- ☆12Aug 12, 2022Updated 3 years ago
- This project aims at designing an easy self-made ultrasound imaging device. It mainly consists of "Phased-array transducer", "Pulse-contr…☆14Jun 28, 2023Updated 2 years ago
- System on Chip verified with UVM/OSVVM/FV☆32Jan 27, 2026Updated last month
- ☆308Jan 23, 2026Updated last month
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆36Dec 24, 2020Updated 5 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆33Feb 6, 2020Updated 6 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Mar 14, 2021Updated 4 years ago