jijingg / Spinal-bootcamp
SpinalHDL-tutorial based on Jupyter Notebook
☆130Updated 8 months ago
Alternatives and similar repositories for Spinal-bootcamp:
Users that are interested in Spinal-bootcamp are comparing it to the libraries listed below
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆113Updated 2 years ago
- Labs to learn SpinalHDL☆146Updated 7 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆204Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆131Updated 2 months ago
- ☆63Updated 2 years ago
- AHB3-Lite Interconnect☆83Updated 9 months ago
- ☆114Updated last week
- SDRAM controller with AXI4 interface☆87Updated 5 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆102Updated 2 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆186Updated last year
- AXI协议规范中文翻译版☆138Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- RTL Verilog library for various DSP modules☆84Updated 3 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- ☆60Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- A basic SpinalHDL project☆81Updated 2 months ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆88Updated last year
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆68Updated 3 years ago
- AXI DMA 32 / 64 bits☆106Updated 10 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆56Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆96Updated 3 years ago
- FFT generator using Chisel☆57Updated 3 years ago
- AXI interface modules for Cocotb☆233Updated last year
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆300Updated 9 months ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆125Updated 5 years ago
- ☆38Updated 2 years ago
- Cortex M0 based SoC☆72Updated 3 years ago
- AXI总线连接器☆94Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 6 years ago