MichaelMelkor / Vivado_Batch_Mode_Tool

Related projects: ⓘ

• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆26Updated last year
• ljgibbslf / basic_cache_core
  ☆23Updated 4 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆31Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆43Updated 3 months ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆51Updated 8 months ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆39Updated 3 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆29Updated last year
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆41Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆44Updated 4 months ago
• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆30Updated 5 years ago
• pulp-platform / fpu
  ☆35Updated 5 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆16Updated 5 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆41Updated last year
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆14Updated 4 years ago
• enjoy-digital / litex_verilog_axi_test
  Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.
  ☆14Updated last year
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 6 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆38Updated last year
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆46Updated last year
• chipsalliance / aib-protocols
  ☆22Updated 7 months ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆28Updated 4 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆27Updated 5 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆15Updated 5 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆24Updated 4 months ago
• maswx / vu13p_corundum
  corundum work on vu13p
  ☆17Updated 10 months ago
• open-dv / dma_axi
  ☆16Updated 5 years ago
• zhaishaomin / ring_network-based-multicore-
  多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
  ☆21Updated 8 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆62Updated 4 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆63Updated 9 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆12Updated 2 months ago