thuCGRA / SpinalHDL_Chinese_DocLinks
Translated SpinalHDL-Doc(v1.7.2) into Chinese
☆51Updated 2 years ago
Alternatives and similar repositories for SpinalHDL_Chinese_Doc
Users that are interested in SpinalHDL_Chinese_Doc are comparing it to the libraries listed below
Sorting:
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- FFT generator using Chisel☆62Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- understanding of cocotb (In Chinese Only)☆19Updated 5 months ago
- ☆65Updated 3 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆145Updated last year
- RTL Verilog library for various DSP modules☆91Updated 3 years ago
- Implement a bitonic sorting network on FPGA☆46Updated 4 years ago
- Open IP in Hardware Description Language.☆28Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆178Updated 2 months ago
- AXI总线连接器☆105Updated 5 years ago
- A tool for those who want to use Vivado's batch mode more easily☆17Updated 5 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆143Updated 2 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆112Updated 3 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- AXI协议规范中文翻译版☆165Updated 3 years ago
- All digital PLL☆28Updated 7 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆107Updated 2 years ago
- ☆79Updated 3 years ago
- CNN accelerator implemented with Spinal HDL☆154Updated last year
- Bitmap Processing Library & AXI-Stream Video Image VIP☆34Updated 3 years ago