thuCGRA / SpinalHDL_Chinese_DocLinks
Translated SpinalHDL-Doc(v1.7.2) into Chinese
☆49Updated 2 years ago
Alternatives and similar repositories for SpinalHDL_Chinese_Doc
Users that are interested in SpinalHDL_Chinese_Doc are comparing it to the libraries listed below
Sorting:
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- FFT generator using Chisel☆60Updated 3 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- A tool for those who want to use Vivado's batch mode more easily☆17Updated 5 years ago
- understanding of cocotb (In Chinese Only)☆17Updated 2 weeks ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆57Updated this week
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- ☆23Updated 2 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- Implement a bitonic sorting network on FPGA☆45Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 10 months ago
- ☆50Updated 6 years ago
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- Some useful documents of Synopsys☆75Updated 3 years ago
- Pure digital components of a UCIe controller☆63Updated this week
- Open IP in Hardware Description Language.☆24Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆34Updated 6 years ago
- ☆55Updated 2 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆75Updated 7 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆138Updated last year
- AXI总线连接器☆98Updated 5 years ago
- This is the repository for the IEEE version of the book☆66Updated 4 years ago