datenlord / poseidon-spinalLinks
The hardware implementation of Poseidon hash function in SpinalHDL
☆19Updated 3 years ago
Alternatives and similar repositories for poseidon-spinal
Users that are interested in poseidon-spinal are comparing it to the libraries listed below
Sorting:
- A Hardware Implemented Poseidon Hasher☆18Updated 3 years ago
- Chisel module for performing Multi-Scalar Multiplication☆13Updated 3 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆32Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆64Updated last year
- ☆81Updated last year
- Hardware Description Language Translator☆17Updated 2 months ago
- FIPS 202 compliant SHA-3 core in Verilog☆22Updated 4 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆19Updated 2 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆46Updated 10 years ago
- Original test vector of RISC-V Vector Extension☆14Updated 4 years ago
- Elgamal's over Elliptic Curves☆19Updated 6 years ago
- Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introd…☆28Updated 4 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Generic Register Interface (contains various adapters)☆125Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 months ago
- For contributions of Chisel IP to the chisel community.☆64Updated 9 months ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆55Updated last month
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated this week
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆63Updated 6 months ago
- Vector processor for RISC-V vector ISA☆125Updated 4 years ago
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现，基为2，有两个并行的蝶形单元☆19Updated 2 years ago
- An out-of-order processor that supports multiple instruction sets.☆19Updated 2 years ago
- SpinalHDL - Cryptography libraries☆56Updated last year
- FPT: a Fixed-Point Accelerator for Torus Fully Homomorphic Encryption☆25Updated 11 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- An open-source custom cache generator.☆34Updated last year