datenlord / poseidon-spinalLinks
The hardware implementation of Poseidon hash function in SpinalHDL
☆19Updated 3 years ago
Alternatives and similar repositories for poseidon-spinal
Users that are interested in poseidon-spinal are comparing it to the libraries listed below
Sorting:
- A Hardware Implemented Poseidon Hasher☆18Updated 3 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆31Updated last year
- Chisel module for performing Multi-Scalar Multiplication☆12Updated 3 years ago
- ☆81Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆21Updated 3 years ago
- RISC-V Functional ISA Simulator☆16Updated 11 months ago
- FIPS 202 compliant SHA-3 core in Verilog☆20Updated 4 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 3 weeks ago
- AXI X-Bar☆19Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 weeks ago
- DDR4 Simulation Project in System Verilog☆41Updated 10 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆13Updated 8 years ago
- Wraps the NVDLA project for Chipyard integration☆20Updated last month
- SpinalHDL - Cryptography libraries☆55Updated 10 months ago
- ☆13Updated 10 years ago
- Hardware Description Language Translator☆16Updated last week
- Run Rocket Chip on VCU128☆30Updated 6 months ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- RTL blocks compatible with the Rocket Chip Generator☆16Updated 2 months ago
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆37Updated 3 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆16Updated 2 years ago