Alternatives and similar repositories for math:

Users that are interested in math are comparing it to the libraries listed below

• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 3 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 7 months ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆91Updated 4 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆73Updated this week
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆133Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆73Updated 2 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆144Updated 10 months ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆77Updated 5 months ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆56Updated 4 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆114Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆53Updated 2 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆102Updated 3 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆68Updated 2 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated last month
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆80Updated this week
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆45Updated 5 months ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆61Updated last year
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated 10 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆88Updated this week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆112Updated last year
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆102Updated 2 years ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆82Updated last year
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆165Updated 4 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 2 months ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆133Updated 2 weeks ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆110Updated 3 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆115Updated this week
• freecores / round_robin_arbiter
  round robin arbiter
  ☆72Updated 10 years ago