Alternatives and similar repositories for dirv

Users that are interested in dirv are comparing it to the libraries listed below

• pezy-computing / pzbcm
  Basic Common Modules
  ☆41Updated last month
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆38Updated 5 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆33Updated 2 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆42Updated 5 months ago
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆21Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆115Updated 3 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆77Updated 9 years ago
• pulp-platform / ace
  ☆16Updated 2 weeks ago
• thiemchu / rvcorep
  ☆10Updated 3 years ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆22Updated 2 months ago
• pulp-platform / axi_llc
  ☆30Updated last week
• pulp-platform / axi2apb
  ☆20Updated 5 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• IObundle / iob-versat
  Coarse Grained Reconfigurable Array
  ☆19Updated 5 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆29Updated last month
• ryuz / jelly
  Original FPGA platform
  ☆68Updated last week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆65Updated 2 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆41Updated 2 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated 11 months ago
• kammoh / chisel-arithmetics
  Implementation of low-level hardware arithmatic operations in Chisel
  ☆7Updated 4 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆30Updated 8 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆45Updated 3 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆49Updated 8 months ago
• ved-rivos / iommu-rtl
  RISC-V IOMMU in verilog
  ☆17Updated 3 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• tenstorrent / cosim-arch-checker
  Framework to perform DUT vs ISS (Whisper) lockstep architectural checks
  ☆18Updated 4 months ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆29Updated 6 years ago