diningyo / dirvLinks
This is my first trial project for designing RISC-V in Chisel
☆17Updated last year
Alternatives and similar repositories for dirv
Users that are interested in dirv are comparing it to the libraries listed below
Sorting:
- Basic Common Modules☆38Updated 2 weeks ago
- RISC-V RV32IMAFC Core for MCU☆37Updated 4 months ago
- The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.☆45Updated 4 years ago
- SystemVerilog language server client for Visual Studio Code☆21Updated 2 years ago
- みんなのSystemVerilog☆19Updated 3 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- Platform Level Interrupt Controller☆40Updated last year
- Original FPGA platform☆65Updated this week
- 10G Ethernet MAC implementation☆21Updated 4 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- FPGA Magazine No.18 - RISC-V☆17Updated 7 years ago
- Coarse Grained Reconfigurable Array☆19Updated 4 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 10 months ago
- ☆36Updated 2 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- Implementation of low-level hardware arithmatic operations in Chisel☆7Updated 3 months ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ☆38Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last year
- (System)Verilog to Chisel translator☆114Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated 2 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆32Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- A RISC-V processor☆15Updated 6 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago