chipsalliance / rocket-chip-inclusive-cacheLinks
An RTL generator for a last-level shared inclusive TileLink cache controller
☆19Updated 5 months ago
Alternatives and similar repositories for rocket-chip-inclusive-cache
Users that are interested in rocket-chip-inclusive-cache are comparing it to the libraries listed below
Sorting:
- A Rocket-based RISC-V superscalar in-order core☆33Updated last month
- This repo includes XiangShan's function units☆26Updated 2 weeks ago
- Open-source non-blocking L2 cache☆43Updated this week
- ☆33Updated 3 months ago
- For contributions of Chisel IP to the chisel community.☆62Updated 7 months ago
- Open source high performance IEEE-754 floating unit☆75Updated last year
- A Scala library for Context-Dependent Environments☆47Updated last year
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆13Updated 4 months ago
- chipyard in mill :P☆78Updated last year
- Open-source high-performance non-blocking cache☆83Updated 3 weeks ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆45Updated 7 months ago
- ☆68Updated 4 months ago
- The 'missing header' for Chisel☆20Updated 3 months ago
- ☆18Updated 2 years ago
- ☆40Updated 2 weeks ago
- Chisel RISC-V Vector 1.0 Implementation☆101Updated last month
- Pure digital components of a UCIe controller☆63Updated this week
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- ☆17Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated last month
- ☆21Updated 3 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Pick your favorite language to verify your chip.☆50Updated last week
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆38Updated last week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Platform Level Interrupt Controller☆41Updated last year