chipsalliance / rocket-chip-inclusive-cache

Related projects: ⓘ

• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆26Updated last month
• sifive / block-inclusivecache-sifive
  ☆71Updated 2 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆31Updated this week
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆13Updated 2 weeks ago
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆44Updated 4 months ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆55Updated 7 months ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆76Updated this week
• chipsalliance / diplomacy
  ☆16Updated 2 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆33Updated this week
• sequencer / arithmetic
  ☆31Updated 7 months ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆40Updated this week
• rameloni / tywaves-chisel-demo
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆19Updated 3 weeks ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆29Updated 2 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆73Updated 9 months ago
• chipsalliance / tilelink
  ☆23Updated 7 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆57Updated 6 months ago
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆31Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆33Updated last year
• esa-tu-darmstadt / SCAIE-V
  An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:
  ☆11Updated 6 months ago
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 2 years ago
• sifive / chisel-circt
  Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
  ☆69Updated last year
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 4 years ago
• OSCPU / chisel-playground
  ☆54Updated 2 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆58Updated 3 weeks ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆29Updated 4 months ago
• Lampro-Mellon / Quasar
  Quasar 2.0: Chisel equivalent of SweRV-EL2
  ☆28Updated 3 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆26Updated 4 months ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• rhit-neuro / deca
  ☆21Updated 3 years ago