chipsalliance / rocket-chip-inclusive-cacheLinks
An RTL generator for a last-level shared inclusive TileLink cache controller
☆19Updated 4 months ago
Alternatives and similar repositories for rocket-chip-inclusive-cache
Users that are interested in rocket-chip-inclusive-cache are comparing it to the libraries listed below
Sorting:
- A Rocket-based RISC-V superscalar in-order core☆33Updated last month
- ☆33Updated 2 months ago
- This repo includes XiangShan's function units☆26Updated this week
- chipyard in mill :P☆78Updated last year
- ☆39Updated last year
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- Open-source non-blocking L2 cache☆43Updated this week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆43Updated 7 months ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 weeks ago
- Open source high performance IEEE-754 floating unit☆72Updated last year
- Open-source high-performance non-blocking cache☆82Updated last week
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆36Updated this week
- A Scala library for Context-Dependent Environments☆47Updated last year
- ☆30Updated 5 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 10 months ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆12Updated 3 months ago
- ☆17Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆77Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆98Updated 3 weeks ago
- ☆21Updated 2 months ago
- Run Rocket Chip on VCU128☆30Updated 6 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆31Updated last year
- Chisel implementation of AES☆23Updated 5 years ago
- Advanced Architecture Labs with CVA6☆61Updated last year
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- An almost empty chisel project as a starting point for hardware design☆31Updated 4 months ago
- Chisel Fixed-Point Arithmetic Library☆14Updated 4 months ago