☆18Jul 3, 2025Updated 9 months ago
Alternatives and similar repositories for wujian100_uvm
Users that are interested in wujian100_uvm are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆23Jun 30, 2025Updated 9 months ago
- ☆10Dec 15, 2023Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆34Dec 11, 2025Updated 4 months ago
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆13Aug 21, 2023Updated 2 years ago
- ☆19May 1, 2023Updated 2 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆38Aug 12, 2015Updated 10 years ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆35Aug 22, 2024Updated last year
- 一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU☆11Oct 8, 2019Updated 6 years ago
- ☆14Jul 28, 2022Updated 3 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆23Apr 25, 2025Updated last year
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- ☆21Sep 26, 2025Updated 7 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆10Jan 3, 2022Updated 4 years ago
- ☆22May 13, 2025Updated 11 months ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated 2 months ago
- ☆17Dec 21, 2020Updated 5 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- study uvm step by step☆11Mar 28, 2019Updated 7 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- Hardware Accelerators on FPGA for Computer Vision Applications☆12Dec 16, 2025Updated 4 months ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆19Feb 27, 2025Updated last year
- SystemVerilog、Verilog、UVM☆16Jun 23, 2020Updated 5 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆15Nov 12, 2025Updated 5 months ago
- UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…☆16Dec 23, 2024Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Constrained RAndom Verification Enviroment (CRAVE)☆19Nov 23, 2023Updated 2 years ago
- 该文档是个人阅读学习蜂鸟E203源码的笔记☆13Aug 1, 2023Updated 2 years ago
- 一个JPEG有损图像压缩编码器☆13May 22, 2023Updated 2 years ago
- Course Project for High Level Chip Design (高层次芯片设计)☆18Jan 2, 2025Updated last year
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- The official NaplesPU hardware code repository☆24Jul 27, 2019Updated 6 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆13Aug 26, 2024Updated last year