Alternatives and similar repositories for SpinalWorkshop

Users that are interested in SpinalWorkshop are comparing it to the libraries listed below

• SpinalHDL / SpinalTemplateSbt
  A basic SpinalHDL project
  ☆86Updated 2 months ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆141Updated last year
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆127Updated 6 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 5 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆185Updated this week
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆122Updated 2 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆125Updated 5 months ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆240Updated last year
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆192Updated 3 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆125Updated 7 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆66Updated last year
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆184Updated 2 weeks ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆110Updated 2 years ago
• SpinalHDL / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆47Updated last year
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆126Updated 10 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• jamieiles / uart
  Verilog UART
  ☆183Updated 12 years ago
• subbdue / systemverilog.io
  Code used in
  ☆197Updated 8 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆179Updated 11 months ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆259Updated 3 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆98Updated last year
• drichmond / RISC-V-On-PYNQ
  RISC-V Integration for PYNQ
  ☆176Updated 6 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆113Updated 3 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆142Updated last week
• SpinalHDL / NaxRiscv
  ☆298Updated last month
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆95Updated 4 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆96Updated 5 years ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆105Updated 2 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆153Updated 6 years ago