Alternatives and similar repositories for SpinalWorkshop:

Users that are interested in SpinalWorkshop are comparing it to the libraries listed below

• SpinalHDL / SpinalTemplateSbt
  A basic SpinalHDL project
  ☆83Updated 2 months ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆132Updated 9 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆210Updated 4 years ago
• SpinalHDL / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆44Updated 11 months ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆126Updated 5 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆172Updated 3 months ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆108Updated last year
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆169Updated 2 years ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆246Updated 2 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆242Updated last year
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆93Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆88Updated 5 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆163Updated 3 months ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆276Updated this week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆134Updated 2 weeks ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆148Updated this week
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆115Updated 5 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated last year
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆181Updated 2 weeks ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆59Updated last year
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆92Updated last year
• SpinalHDL / NaxRiscv
  ☆275Updated this week
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆153Updated last year
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆146Updated 4 months ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆234Updated 10 months ago
• leros-dev / leros
  A Tiny Processor Core
  ☆107Updated this week
• ucb-bar / berkeley-hardfloat
  ☆310Updated 6 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆136Updated 3 weeks ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆127Updated last year
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆96Updated 3 years ago