SpinalHDL / SpinalWorkshopLinks
Labs to learn SpinalHDL
☆149Updated last year
Alternatives and similar repositories for SpinalWorkshop
Users that are interested in SpinalWorkshop are comparing it to the libraries listed below
Sorting:
- A basic SpinalHDL project☆87Updated 3 months ago
- SpinalHDL-tutorial based on Jupyter Notebook☆138Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆218Updated 4 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 5 years ago
- Various caches written in Verilog-HDL☆125Updated 10 years ago
- Code used in☆193Updated 8 years ago
- Network on Chip Implementation written in SytemVerilog☆186Updated 2 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Verilog UART☆177Updated 12 years ago
- Basic RISC-V Test SoC☆138Updated 6 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆64Updated last year
- A Tiny Processor Core☆110Updated 3 weeks ago
- Verilog Configurable Cache☆180Updated 8 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆138Updated 2 weeks ago
- Chisel examples and code snippets☆255Updated 3 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆236Updated last year
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆168Updated last week
- ☆293Updated 3 weeks ago
- An AXI4 crossbar implementation in SystemVerilog☆164Updated last month
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆171Updated 8 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆122Updated 2 months ago
- A Fast, Low-Overhead On-chip Network☆220Updated this week
- Chisel Learning Journey☆109Updated 2 years ago
- A simple implementation of a UART modem in Verilog.☆148Updated 3 years ago
- Vector processor for RISC-V vector ISA☆122Updated 4 years ago
- SDRAM controller with AXI4 interface☆96Updated 5 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆45Updated last year
- Provides dot visualizations of chisel/firrtl circuits☆120Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago