Alternatives and similar repositories for SpinalHDLDemo:

Users that are interested in SpinalHDLDemo are comparing it to the libraries listed below

• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆84Updated 2 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆30Updated 4 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆36Updated 7 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆28Updated 2 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆35Updated 9 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 4 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆52Updated 10 years ago
• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆31Updated 5 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆57Updated last year
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆88Updated 4 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆32Updated this week
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆37Updated 2 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆52Updated 8 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• JefferyLi0903 / MMC
  MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计
  ☆21Updated last year
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆28Updated 5 years ago
• RicardoNid / ChainsawOld
  ☆23Updated 2 years ago
• DawnCarol / OpenC910_Modified
  commit rtl and build cosim env
  ☆13Updated 11 months ago
• pulp-platform / axi_spi_master
  ☆20Updated 5 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆30Updated 6 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆18Updated 5 years ago
• antmicro / nvme-verilog-pcie
  ☆53Updated 2 years ago
• wanderingnail / AXI_DMA
  ☆16Updated 2 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆28Updated 3 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆70Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆61Updated 4 years ago
• Noris4est / I2C-FPGA-Verilog-HDL
  In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…
  ☆14Updated 4 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆57Updated 11 months ago