balanx / SpinalHDLDemo
Demo Sources for Learning Spinal HDL
☆15Updated 2 years ago
Alternatives and similar repositories for SpinalHDLDemo
Users that are interested in SpinalHDLDemo are comparing it to the libraries listed below
Sorting:
- 学习AXI接口,以及xilinx DDR3 IP使用☆36Updated 8 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆37Updated 3 years ago
- I2C Master and Slave☆33Updated 9 years ago
- ☆30Updated 5 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- ☆21Updated 5 years ago
- FFT implement by verilog_测试验证已通过☆55Updated 8 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- Must-have verilog systemverilog modules☆34Updated 3 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆24Updated last year
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- Cortex M0 based SoC☆73Updated 3 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆17Updated 5 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- Verilog SPI master and slave☆53Updated 9 years ago
- ☆59Updated 2 years ago
- ☆67Updated 3 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆17Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Generic AXI to AHB bridge☆17Updated 10 years ago
- ☆36Updated 9 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆74Updated 2 years ago