SpinalHDL / VexRiscvSocSoftwareLinks
☆26Updated 3 years ago
Alternatives and similar repositories for VexRiscvSocSoftware
Users that are interested in VexRiscvSocSoftware are comparing it to the libraries listed below
Sorting:
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 4 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆125Updated 5 months ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆127Updated 6 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆47Updated 3 years ago
- A basic SpinalHDL project☆86Updated 2 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆50Updated last year
- Spen's Official OpenOCD Mirror☆50Updated 7 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆70Updated last year
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- ☆27Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 3 weeks ago
- ☆96Updated 2 months ago
- ☆40Updated last year
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆67Updated 5 months ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 9 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- Platform Level Interrupt Controller☆43Updated last year
- A demo system for Ibex including debug support and some peripherals☆78Updated 4 months ago
- PCI Express controller model☆68Updated 3 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆121Updated last week
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- RISC-V Nox core☆68Updated 3 months ago
- Verilog implementation of a RISC-V core☆125Updated 7 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆67Updated 11 months ago