Alternatives and similar repositories for proteus:

Users that are interested in proteus are comparing it to the libraries listed below

• chipsalliance / tilelink
  ☆28Updated 3 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 8 months ago
• RPTU-EIS / upec-boom-verification-suite
  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…
  ☆17Updated 2 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆63Updated 9 months ago
• ucb-bar / sha3
  ☆78Updated last year
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 4 years ago
• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆36Updated last month
• samehattia / StateMover
  StateMover is a checkpoint-based debugging framework for FPGAs.
  ☆19Updated 2 years ago
• riscv-non-isa / tg-nexus-trace
  RISC-V Nexus Trace TG documentation and reference code
  ☆50Updated 2 months ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆84Updated this week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆54Updated last year
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆25Updated 5 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆45Updated 4 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆37Updated 10 months ago
• ved-rivos / iommu-rtl
  RISC-V IOMMU in verilog
  ☆17Updated 2 years ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆88Updated this week
• riscv / riscv-CMOs
  ☆85Updated 2 years ago
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆19Updated last year
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆62Updated 2 weeks ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆129Updated last week
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆30Updated 10 months ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆31Updated 3 years ago
• hushenwei2000 / rvv-atg
  RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…
  ☆14Updated 11 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 10 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆85Updated last week
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆109Updated last week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆112Updated 2 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆48Updated 2 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 4 years ago