Alternatives and similar repositories for SpinalHDL-ethernet

Users that are interested in SpinalHDL-ethernet are comparing it to the libraries listed below

• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆32Updated last year
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated last year
• freechipsproject / chisel-cheatsheet
  Chisel Cheatsheet
  ☆34Updated 2 years ago
• FPGA-House-AG / SpinalCorundum
  SpinalHDL components for Corundum Ethernet
  ☆13Updated 2 years ago
• SchaffHub / RISC-Verdi
  Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.
  ☆33Updated 5 years ago
• fayalalebrun / awesome-spinalhdl
  List of SpinalHDL projects, libraries, and learning resources.
  ☆20Updated 8 months ago
• sequencer / arithmetic
  ☆33Updated 9 months ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆26Updated 2 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆69Updated last year
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆50Updated 5 months ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆51Updated 2 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆71Updated 3 weeks ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆43Updated 11 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆21Updated 7 months ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆31Updated last year
• pulp-platform / axi_llc
  ☆32Updated 3 weeks ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆55Updated 2 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated 11 months ago
• spike556 / HuffmanCode
  hardware implement of huffman coding(written in verilog)
  ☆14Updated 8 years ago
• maswx / vu13p_corundum
  corundum work on vu13p
  ☆22Updated 2 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆71Updated 3 years ago
• ucb-bar / chisel-gui
  A prototype GUI for chisel-development
  ☆51Updated 5 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆35Updated 3 weeks ago
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆29Updated 5 years ago
• SpinalHDL / SpinalCrypto
  SpinalHDL - Cryptography libraries
  ☆57Updated last year
• Angelic47 / GowinDDR3_AXI4_SpinalHDL
  Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现
  ☆27Updated last year
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆71Updated 7 months ago
• oprecomp / DDR4_controller
  ☆69Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated last week