mwrnd / notes

Related projects ⓘ

Alternatives and complementary repositories for notes

• fpgasystems / davos
  Distributed Accelerator OS
  ☆60Updated 2 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆93Updated this week
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆102Updated 2 years ago
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆142Updated 2 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆40Updated last year
• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆78Updated 2 years ago
• Xilinx / HLS_packet_processing
  ☆45Updated 4 years ago
• oprecomp / DDR4_controller
  ☆47Updated 3 years ago
• yhqiu16 / NVMeCHA
  NVMe Controller featuring Hardware Acceleration
  ☆76Updated 3 years ago
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆122Updated 3 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆60Updated this week
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆54Updated 4 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆46Updated 2 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆95Updated last year
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆41Updated 3 years ago
• sangwoojun / bluespecpcie
  PCIe library for the Xilinx 7 series FPGAs in the Bluespec language
  ☆72Updated 2 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆67Updated 5 months ago
• ATaylorCEngFIET / Vitis_Hero
  ☆24Updated 2 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆49Updated 4 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆80Updated last year
• yu-zou / DirectNVM
  An open-source RTL NVMe controller IP for Xilinx FPGA.
  ☆40Updated 3 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆158Updated 2 years ago
• Xilinx / pcie_qdma_ats_example
  ☆22Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆54Updated last year
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆68Updated 6 years ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆25Updated this week
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆59Updated last month
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆184Updated 6 months ago
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆47Updated 8 years ago