Alternatives and similar repositories for NaxRiscv:

Users that are interested in NaxRiscv are comparing it to the libraries listed below

• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆273Updated last year
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆148Updated this week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆222Updated 3 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 4 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆239Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆459Updated last month
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆266Updated this week
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆210Updated 4 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆246Updated 4 months ago
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆230Updated last week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆183Updated 8 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆205Updated last week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆181Updated last week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆173Updated last year
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆246Updated last week
• ucb-bar / berkeley-hardfloat
  ☆309Updated 6 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆172Updated 3 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆583Updated last week
• RoaLogic / RV12
  RISC-V CPU Core
  ☆317Updated 9 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆308Updated 3 months ago
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆231Updated 6 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆168Updated last year
• chipsalliance / Cores-VeeR-EH2
  ☆229Updated 2 years ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆156Updated this week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆169Updated 7 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆150Updated 2 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆183Updated this week
• subbdue / systemverilog.io
  Code used in
  ☆179Updated 7 years ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆146Updated 8 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆502Updated this week