SpinalHDL / NaxRiscv
☆279Updated last week
Alternatives and similar repositories for NaxRiscv:
Users that are interested in NaxRiscv are comparing it to the libraries listed below
- RISC-V RV64GC emulator designed for RTL co-simulation☆223Updated 4 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆149Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆249Updated 2 weeks ago
- RISC-V Debug Support for our PULP RISC-V Cores☆247Updated 4 months ago
- VeeR EL2 Core☆268Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆461Updated last month
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 4 months ago
- CORE-V Family of RISC-V Cores☆246Updated last month
- Instruction Set Generator initially contributed by Futurewei☆274Updated last year
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆234Updated this week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆210Updated 4 years ago
- Common SystemVerilog components☆590Updated this week
- ☆169Updated last year
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆206Updated last week
- RISC-V Torture Test☆186Updated 8 months ago
- ☆310Updated 6 months ago
- ☆231Updated 2 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆173Updated last year
- A Fast, Low-Overhead On-chip Network☆182Updated this week
- FuseSoC-based SoC for VeeR EH1 and EL2☆308Updated 3 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆560Updated this week
- A Linux-capable RISC-V multicore for and by the world☆669Updated 3 weeks ago
- RISC-V microcontroller IP core developed in Verilog☆169Updated this week
- RISC-V CPU Core☆317Updated 9 months ago
- SystemVerilog synthesis tool☆181Updated last week
- Functional verification project for the CORE-V family of RISC-V cores.☆506Updated this week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆326Updated this week
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆231Updated 7 months ago
- Verilog Configurable Cache☆174Updated 3 months ago
- SoC based on VexRiscv and ICE40 UP5K☆154Updated last week