Alternatives and similar repositories for NaxRiscv

Users that are interested in NaxRiscv are comparing it to the libraries listed below

• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆175Updated last week
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆282Updated this week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆293Updated 7 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆244Updated 10 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 9 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆293Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆270Updated 4 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆297Updated 2 weeks ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆196Updated last year
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆524Updated last week
• chipsalliance / Cores-VeeR-EH2
  ☆244Updated 2 years ago
• ucb-bar / berkeley-hardfloat
  ☆341Updated last year
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 5 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆181Updated 9 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆187Updated last year
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆218Updated 3 months ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆214Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆209Updated 6 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆265Updated 2 weeks ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated last month
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆147Updated last week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆324Updated 9 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆177Updated 4 months ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆179Updated 5 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆224Updated last month
• RoaLogic / RV12
  RISC-V CPU Core
  ☆375Updated 2 months ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆151Updated last year
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆304Updated this week
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆406Updated last week