SpinalHDL / NaxRiscvLinks
☆300Updated 3 weeks ago
Alternatives and similar repositories for NaxRiscv
Users that are interested in NaxRiscv are comparing it to the libraries listed below
Sorting:
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆190Updated 3 weeks ago
- Instruction Set Generator initially contributed by Futurewei☆302Updated 2 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆235Updated last year
- CORE-V Family of RISC-V Cores☆308Updated 9 months ago
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆302Updated this week
- RISC-V Torture Test☆204Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆246Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆283Updated last week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- VeeR EL2 Core☆305Updated 2 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆544Updated last month
- ☆358Updated 2 months ago
- RISC-V System on Chip Template☆159Updated 3 months ago
- Verilog Configurable Cache☆186Updated last week
- FuseSoC-based SoC for VeeR EH1 and EL2☆331Updated 11 months ago
- ☆250Updated 2 years ago
- ☆190Updated last year
- RISC-V CPU Core☆394Updated 5 months ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆228Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆275Updated 2 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆219Updated 3 weeks ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆192Updated this week
- SystemVerilog synthesis tool☆219Updated 8 months ago
- A Fast, Low-Overhead On-chip Network☆247Updated this week
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆312Updated 2 weeks ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆232Updated last year
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆198Updated last week
- RISC-V soft-core microcontroller for FPGA implementation☆187Updated last week
- Labs to learn SpinalHDL☆150Updated last year
- Code used in☆198Updated 8 years ago