SpinalHDL-tutorial based on Jupyter Notebook
☆47Apr 9, 2024Updated last year
Alternatives and similar repositories for Spinal-bootcamp
Users that are interested in Spinal-bootcamp are comparing it to the libraries listed below
Sorting:
- A basic SpinalHDL project☆90Aug 15, 2025Updated 6 months ago
- Labs to learn SpinalHDL☆154Jul 4, 2024Updated last year
- Scala based HDL☆1,928Feb 18, 2026Updated last week
- Network components (NIC, Switch) for FireBox☆19Oct 27, 2024Updated last year
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆54Jun 11, 2023Updated 2 years ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- ☆13Feb 13, 2026Updated 2 weeks ago
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 5 years ago
- ☆10Apr 8, 2021Updated 4 years ago
- SDRAM controller for MIPSfpga+ system☆24Oct 30, 2020Updated 5 years ago
- ☆27Dec 15, 2021Updated 4 years ago
- ☆24May 6, 2023Updated 2 years ago
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- Generic AXI interconnect fabric☆13Jul 17, 2014Updated 11 years ago
- A programming language for FPGAs.☆20May 5, 2018Updated 7 years ago
- A version of f32c/arduino that works with the SpinalHDL Vexriscv Murax SoC☆14May 23, 2019Updated 6 years ago
- SoC based on VexRiscv and ICE40 UP5K☆161Mar 16, 2025Updated 11 months ago
- SpinalHDL - Cryptography libraries☆59Jul 19, 2024Updated last year
- GPU for OENG1167 in Verilog HDL for DE10 series boards☆15Nov 1, 2020Updated 5 years ago
- Chisel HDL example applications☆30Aug 11, 2022Updated 3 years ago
- An open hardware/free software low tech flying-probe tester based on available technology (3D printer mechanics/controller, raspberry pi,…☆15Oct 16, 2020Updated 5 years ago
- SpinalHDL documentation assets (pictures, slides, ...)☆32Dec 10, 2024Updated last year
- For contributions of Chisel IP to the chisel community.☆71Nov 7, 2024Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Feb 23, 2026Updated last week
- APB Logic☆24Updated this week
- Championship Value Prediction (CVP) simulator.☆17Feb 17, 2021Updated 5 years ago
- Parsing library for BLIF netlists☆19Nov 1, 2024Updated last year
- Port of EDK2 implementation of UEFI to RISC-V. See documentation at:☆17Nov 15, 2021Updated 4 years ago
- Rapid Abstraction FPGA Toolbox - Python toolbox which provides direct access to FPGA hardware peripherals☆28Feb 17, 2026Updated last week
- ☆21Feb 15, 2023Updated 3 years ago
- understanding of cocotb (In Chinese Only)☆20Jun 10, 2025Updated 8 months ago
- Tutorial Material from the SST Team☆25Aug 5, 2025Updated 6 months ago
- All Logi specific HDL code (platform specific interface, extension boards, specific hdl, etc)☆31Jan 25, 2016Updated 10 years ago
- ☆18Sep 2, 2020Updated 5 years ago
- RISC-V Nexus Trace TG documentation and reference code☆57Updated this week
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆21Dec 23, 2024Updated last year
- Docker Development Environment for SpinalHDL☆20Aug 8, 2024Updated last year
- List of SpinalHDL projects, libraries, and learning resources.☆25Jan 6, 2026Updated last month
- ☆23Oct 1, 2022Updated 3 years ago