SpinalHDL / Spinal-bootcampLinks
SpinalHDL-tutorial based on Jupyter Notebook
☆45Updated last year
Alternatives and similar repositories for Spinal-bootcamp
Users that are interested in Spinal-bootcamp are comparing it to the libraries listed below
Sorting:
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- A basic SpinalHDL project☆88Updated 2 months ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆49Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆61Updated 5 months ago
- Labs to learn SpinalHDL☆148Updated 11 months ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆105Updated last month
- For contributions of Chisel IP to the chisel community.☆62Updated 7 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 7 months ago
- SpinalHDL-tutorial based on Jupyter Notebook☆138Updated last year
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- ☆59Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆136Updated last week
- openHMC - an open source Hybrid Memory Cube Controller☆49Updated 9 years ago
- Platform Level Interrupt Controller☆41Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆57Updated last week
- Home of the Advanced Interface Bus (AIB) specification.☆52Updated 2 years ago
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- Pure digital components of a UCIe controller☆63Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆64Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- Simple single-port AXI memory interface☆41Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- Verilog Ethernet Switch (layer 2)☆44Updated last year
- ☆96Updated last year
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago