Alternatives and similar repositories for SpinalCrypto

Users that are interested in SpinalCrypto are comparing it to the libraries listed below

• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 3 weeks ago
• SpinalHDL / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆47Updated last year
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆67Updated 6 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆181Updated 7 months ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated last year
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 4 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆134Updated last month
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆94Updated 2 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆128Updated 7 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆110Updated 2 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆189Updated 3 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 9 months ago
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆210Updated last year
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆50Updated 9 years ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆105Updated last month
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆144Updated last year
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆59Updated 2 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆89Updated last year
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆128Updated 2 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆53Updated 5 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆100Updated 2 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• malkadi / FGPU
  FGPU is a soft GPU architecture general purpose computing
  ☆60Updated 5 years ago