Alternatives and similar repositories for chisel-template

Users that are interested in chisel-template are comparing it to the libraries listed below

• schoeberl / chisel-book
  Digital Design with Chisel
  ☆894Updated this week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆603Updated last year
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆743Updated 4 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,107Updated last year
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆734Updated 5 months ago
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆266Updated 3 years ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆748Updated last year
• ucb-bar / berkeley-hardfloat
  ☆367Updated 4 months ago
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆371Updated 8 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆568Updated 3 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆706Updated this week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆539Updated last year
• ucb-bar / chiseltest
  The batteries-included testing and formal verification library for Chisel-based RTL designs.
  ☆233Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,176Updated 8 months ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆717Updated 2 years ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆485Updated 2 months ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆922Updated 2 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆223Updated this week
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆344Updated 8 years ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,487Updated last week
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,133Updated this week
• XUANTIE-RV / openc910
  OpenXuantie - OpenC910 Core
  ☆1,387Updated last year
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,248Updated 4 months ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,176Updated 4 years ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆457Updated 8 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆766Updated 4 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆653Updated this week
• riscv-software-src / riscv-tests
  ☆1,117Updated 2 weeks ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆699Updated 2 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆641Updated 2 weeks ago