firesim / icenetLinks
Network components (NIC, Switch) for FireBox
☆19Updated last year
Alternatives and similar repositories for icenet
Users that are interested in icenet are comparing it to the libraries listed below
Sorting:
- Chisel/Firrtl execution engine☆153Updated last year
- ☆87Updated 3 weeks ago
- Wrapper for ETH Ariane Core☆21Updated 2 months ago
- A scala based simulator for circuits described by a LoFirrtl file☆49Updated 2 years ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆22Updated 10 months ago
- A Scala library for Context-Dependent Environments☆49Updated last year
- Useful utilities for BAR projects☆32Updated last year
- A Rocket-based RISC-V superscalar in-order core☆36Updated last month
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 6 years ago
- DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language☆92Updated this week
- RTL blocks compatible with the Rocket Chip Generator☆16Updated 7 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Provides various testers for chisel users☆100Updated 2 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆37Updated 2 months ago
- An implementation of RISC-V☆43Updated last month
- A coverage library for Chisel designs☆11Updated 5 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- For contributions of Chisel IP to the chisel community.☆67Updated last year
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆156Updated last year
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆89Updated 6 years ago
- Block-diagram style digital logic visualizer☆23Updated 10 years ago
- BSC Development Workstation (BDW)☆32Updated 2 weeks ago
- Generic Register Interface (contains various adapters)☆133Updated last month
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆86Updated last month
- ☆11Updated 3 years ago
- A home for Genesis2 sources.☆43Updated 4 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆50Updated 10 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆29Updated last week
- pulp_soc is the core building component of PULP based SoCs☆81Updated 8 months ago