Alternatives and similar repositories for icenet:

Users that are interested in icenet are comparing it to the libraries listed below

• ucb-bar / cva6-wrapper
  Wrapper for ETH Ariane Core
  ☆19Updated 6 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆29Updated 2 weeks ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆31Updated last year
• ucb-bar / testchipip
  ☆82Updated last week
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆47Updated 9 months ago
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆154Updated 6 months ago
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated 2 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 10 years ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆84Updated this week
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆47Updated 2 years ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆99Updated 5 years ago
• IBM / perfect-chisel
  Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
  ☆30Updated 2 years ago
• sifive / soc-freedom-sifive
  e300 and u500 devkits
  ☆10Updated 4 years ago
• bespoke-silicon-group / bsg_replicant
  BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade
  ☆29Updated this week
• sifive / fpga-shells
  ☆133Updated 2 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• sifive / chisel-circt
  Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
  ☆71Updated last year
• pulp-platform / redmule
  ☆42Updated this week
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆14Updated 7 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆60Updated 5 months ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆120Updated last year
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆46Updated 5 months ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆149Updated last year
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆16Updated last month
• fpgasystems / fpga-hyperloglog
  FPGA-based HyperLogLog Accelerator
  ☆12Updated 4 years ago