Alternatives and similar repositories for SaxonSoc

Users that are interested in SaxonSoc are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆150Updated 2 weeks ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆189Updated last week
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆133Updated 7 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆194Updated last week
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆281Updated last year
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆186Updated last year
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆298Updated this week
• olofk / corescore
  CoreScore
  ☆171Updated last month
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆92Updated 2 months ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆144Updated 2 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆318Updated last year
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆128Updated 7 months ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆124Updated 5 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆185Updated last year
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆159Updated last year
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆102Updated 3 weeks ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆250Updated last year
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆319Updated last month
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆249Updated last year
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆118Updated 4 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆309Updated this week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆335Updated last year
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆86Updated last week
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆310Updated 10 months ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆182Updated this week
• ZipCPU / vgasim
  A Video display simulator
  ☆174Updated 7 months ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆460Updated 3 weeks ago