Alternatives and similar repositories for SaxonSoc

Users that are interested in SaxonSoc are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆146Updated 2 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆122Updated 6 years ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆179Updated 2 months ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆182Updated 7 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆122Updated 2 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated 3 weeks ago
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆182Updated 2 weeks ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆293Updated last week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆245Updated 9 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆307Updated last year
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated last week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆321Updated 7 months ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆312Updated last week
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 10 months ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆431Updated last month
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆130Updated last year
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆85Updated 2 weeks ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆283Updated 5 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆292Updated 2 weeks ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆121Updated 4 years ago
• olofk / corescore
  CoreScore
  ☆159Updated 6 months ago
• SpinalHDL / NaxRiscv
  ☆293Updated 3 weeks ago
• ZipCPU / vgasim
  A Video display simulator
  ☆171Updated 2 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆272Updated 5 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆278Updated 11 months ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆175Updated last year
• stnolting / neorv32-setups
  📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
  ☆78Updated last week
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆181Updated this week