SpinalHDL / SaxonSocLinks
SoC based on VexRiscv and ICE40 UP5K
☆158Updated 7 months ago
Alternatives and similar repositories for SaxonSoc
Users that are interested in SaxonSoc are comparing it to the libraries listed below
Sorting:
- FuseSoC standard core library☆148Updated 5 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆125Updated 5 months ago
- Verilog implementation of a RISC-V core☆128Updated 7 years ago
- Example LED blinking project for your FPGA dev board of choice☆186Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆122Updated 4 months ago
- Example designs showing different ways to use F4PGA toolchains.☆276Updated last year
- CoreScore☆167Updated 3 weeks ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated last month
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- A simple, basic, formally verified UART controller☆314Updated last year
- Yet Another RISC-V Implementation☆98Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆246Updated last year
- A 32-bit RISC-V soft processor☆316Updated 3 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated this week
- Naive Educational RISC V processor☆91Updated last month
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆295Updated this week
- Experimental flows using nextpnr for Xilinx devices☆245Updated last year
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆123Updated 5 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆331Updated 11 months ago
- ☆300Updated this week
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆183Updated last year
- A Video display simulator☆174Updated 5 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆190Updated this week
- CORE-V Family of RISC-V Cores☆304Updated 9 months ago
- VeeR EL2 Core☆303Updated this week
- An Open Source configuration of the Arty platform☆132Updated last year
- A simple RISC-V processor for use in FPGA designs.☆281Updated last year
- ☆137Updated 11 months ago