SpinalHDL / SaxonSoc
SoC based on VexRiscv and ICE40 UP5K
☆154Updated last week
Alternatives and similar repositories for SaxonSoc:
Users that are interested in SaxonSoc are comparing it to the libraries listed below
- FuseSoC standard core library☆128Updated last month
- Verilog implementation of a RISC-V core☆109Updated 6 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆308Updated 3 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆247Updated 4 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆225Updated 4 months ago
- Experimental flows using nextpnr for Xilinx devices☆228Updated 5 months ago
- Example LED blinking project for your FPGA dev board of choice☆172Updated last month
- VeeR EL2 Core☆268Updated this week
- ☆279Updated 2 weeks ago
- FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.☆280Updated last week
- A simple, basic, formally verified UART controller☆294Updated last year
- Example designs showing different ways to use F4PGA toolchains.☆272Updated 11 months ago
- Labs to learn SpinalHDL☆147Updated 8 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆143Updated 4 months ago
- SystemVerilog synthesis tool☆181Updated 2 weeks ago
- CORE-V Family of RISC-V Cores☆246Updated last month
- Yet Another RISC-V Implementation☆90Updated 6 months ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆173Updated last year
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆114Updated 3 months ago
- RISC-V Verification Interface☆85Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆80Updated this week
- A utility for Composing FPGA designs from Peripherals☆173Updated 3 months ago
- RISC-V System on Chip Template☆156Updated this week
- VHDL library 4 FPGAs☆175Updated this week
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆75Updated 3 years ago
- RISC-V CPU Core☆317Updated 9 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆149Updated this week
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆206Updated last week
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆117Updated 4 years ago
- An Open Source configuration of the Arty platform☆128Updated last year