Alternatives and similar repositories for SaxonSoc

Users that are interested in SaxonSoc are comparing it to the libraries listed below

• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆139Updated last week
• chipsalliance / f4pga-examples
  Example designs showing different ways to use F4PGA toolchains.
  ☆276Updated last year
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆117Updated 6 years ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆175Updated last week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆238Updated 6 months ago
• SpinalHDL / NaxRiscv
  ☆288Updated 2 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated 2 weeks ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆121Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆278Updated last week
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆414Updated last week
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆135Updated 3 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆320Updated 5 months ago
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆288Updated this week
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆116Updated 4 years ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆237Updated 7 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆177Updated last month
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆159Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆257Updated last month
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆179Updated 5 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆303Updated last year
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆269Updated 3 months ago
• olofk / corescore
  CoreScore
  ☆155Updated 4 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 6 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆125Updated 6 years ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆311Updated 3 months ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆214Updated last week
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆130Updated last year
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆165Updated 4 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆238Updated 2 years ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆148Updated 10 months ago