Chainsaw-Team / ChainsawLinks
a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications
☆62Updated last year
Alternatives and similar repositories for Chainsaw
Users that are interested in Chainsaw are comparing it to the libraries listed below
Sorting:
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- General Purpose AXI Direct Memory Access☆50Updated last year
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated this week
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- FFT generator using Chisel☆59Updated 3 years ago
- ☆51Updated 2 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- ☆33Updated 6 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- An AXI4 crossbar implementation in SystemVerilog☆154Updated 3 weeks ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- ☆49Updated 6 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆135Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- SpinalHDL-tutorial based on Jupyter Notebook☆136Updated 11 months ago
- Advanced Architecture Labs with CVA6☆61Updated last year
- Pure digital components of a UCIe controller☆63Updated this week
- understanding of cocotb (In Chinese Only)☆17Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆77Updated this week
- Vector processor for RISC-V vector ISA☆119Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆101Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆47Updated 7 months ago
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- ☆28Updated 4 years ago