Chainsaw-Team / ChainsawView external linksLinks
a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications
☆68Jan 8, 2024Updated 2 years ago
Alternatives and similar repositories for Chainsaw
Users that are interested in Chainsaw are comparing it to the libraries listed below
Sorting:
- ☆21Feb 15, 2023Updated 3 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆53Jun 11, 2023Updated 2 years ago
- [FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic M…☆21May 6, 2024Updated last year
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 2 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆61Jan 7, 2026Updated last month
- CNN accelerator implemented with Spinal HDL☆157Jan 29, 2024Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Feb 2, 2026Updated 2 weeks ago
- Labs to learn SpinalHDL☆153Jul 4, 2024Updated last year
- List of SpinalHDL projects, libraries, and learning resources.☆25Jan 6, 2026Updated last month
- SpinalHDL Hardware Math Library☆96Jul 12, 2024Updated last year
- Scala based HDL☆1,922Updated this week
- The hardware implementation of Poseidon hash function in SpinalHDL☆21Jun 5, 2022Updated 3 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆151Jun 14, 2024Updated last year
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆33Jan 2, 2024Updated 2 years ago
- RISCV lock-step checker based on Spike☆14Jan 23, 2026Updated 3 weeks ago
- The sources of the online SpinalHDL doc☆30Updated this week
- ☆23Oct 1, 2022Updated 3 years ago
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 4 years ago
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 2 months ago
- ☆10Jan 25, 2023Updated 3 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆83Aug 29, 2023Updated 2 years ago
- ☆16Mar 8, 2025Updated 11 months ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated 3 weeks ago
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 6 years ago
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago
- Demo Sources for Learning Spinal HDL☆16Dec 5, 2022Updated 3 years ago
- ☆12Jan 19, 2022Updated 4 years ago
- A basic SpinalHDL project☆90Aug 15, 2025Updated 6 months ago
- A Hardware Implemented Poseidon Hasher☆20Apr 15, 2022Updated 3 years ago
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated last year
- ☆306Jan 23, 2026Updated 3 weeks ago
- understanding of cocotb (In Chinese Only)☆20Jun 10, 2025Updated 8 months ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Mar 14, 2021Updated 4 years ago
- SpinalHDL - Cryptography libraries☆59Jul 19, 2024Updated last year
- Docker Development Environment for SpinalHDL☆20Aug 8, 2024Updated last year
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Apr 9, 2024Updated last year
- 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。☆602Sep 15, 2023Updated 2 years ago
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated 2 weeks ago
- ☆14Oct 11, 2024Updated last year