a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications
☆70Jan 8, 2024Updated 2 years ago
Alternatives and similar repositories for Chainsaw
Users that are interested in Chainsaw are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆23Feb 15, 2023Updated 3 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆63Jun 18, 2026Updated 2 months ago
- [FPL'24] This repository contains the source code for the paper “Revealing Untapped DSP Optimization Potentials for FPGA-based Systolic M…☆23May 6, 2024Updated 2 years ago
- CNN accelerator implemented with Spinal HDL☆160Jan 29, 2024Updated 2 years ago
- SpinalHDL components for Corundum Ethernet☆15Aug 16, 2023Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆56Jun 11, 2023Updated 3 years ago
- Labs to learn SpinalHDL☆157Jul 4, 2024Updated 2 years ago
- Scala based HDL☆2,027Updated this week
- List of SpinalHDL projects, libraries, and learning resources.☆30Jan 6, 2026Updated 7 months ago
- SpinalHDL Hardware Math Library☆103Jul 12, 2024Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆55Feb 2, 2026Updated 6 months ago
- RISCV lock-step checker based on Spike☆16Updated this week
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 8 months ago
- ☆12Jan 19, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆324Jan 23, 2026Updated 6 months ago
- Demo Sources for Learning Spinal HDL☆16Dec 5, 2022Updated 3 years ago
- Docker Development Environment for SpinalHDL☆20Aug 8, 2024Updated 2 years ago
- The hardware implementation of Poseidon hash function in SpinalHDL☆21Jun 5, 2022Updated 4 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆152Jun 14, 2024Updated 2 years ago
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 7 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆38Mar 14, 2021Updated 5 years ago
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated 2 years ago
- SpinalHDL - Cryptography libraries☆62Jul 19, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- The sources of the online SpinalHDL doc☆31Jul 21, 2026Updated 3 weeks ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆100Aug 29, 2023Updated 2 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆244Updated this week
- A basic SpinalHDL project☆98Aug 15, 2025Updated last year
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆39Jan 2, 2024Updated 2 years ago
- ☆24May 6, 2023Updated 3 years ago
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆12Dec 5, 2018Updated 7 years ago
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago
- A Hardware Implemented Poseidon Hasher☆20Apr 15, 2022Updated 4 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Chisel implementation of Neural Processing Unit for System on the Chip☆34Aug 5, 2026Updated last week
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- ☆19Mar 8, 2025Updated last year
- Awesome projects using the Amaranth HDL☆20Feb 6, 2025Updated last year
- ☆10Jan 25, 2023Updated 3 years ago
- This is Max's blog, something interesting in it.☆13Jan 1, 2023Updated 3 years ago
- 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。☆612Sep 15, 2023Updated 2 years ago