Chainsaw-Team / Chainsaw
a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications
☆60Updated last year
Alternatives and similar repositories for Chainsaw:
Users that are interested in Chainsaw are comparing it to the libraries listed below
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- SDRAM controller with AXI4 interface☆89Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆53Updated 2 weeks ago
- General Purpose AXI Direct Memory Access☆48Updated 10 months ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- ☆47Updated 2 years ago
- FFT generator using Chisel☆58Updated 3 years ago
- round robin arbiter☆71Updated 10 years ago
- Pure digital components of a UCIe controller☆59Updated 2 weeks ago
- ☆31Updated 5 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆101Updated 3 years ago
- ☆57Updated 2 years ago
- An AXI4 crossbar implementation in SystemVerilog☆140Updated last month
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- ☆64Updated 2 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆44Updated 11 months ago
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆164Updated 4 months ago
- A basic SpinalHDL project☆83Updated 2 weeks ago
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆63Updated 3 months ago
- SpinalHDL-tutorial based on Jupyter Notebook☆132Updated 9 months ago
- AMBA bus generator including AXI, AHB, and APB☆99Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- ☆23Updated 2 years ago
- ☆53Updated 4 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆93Updated last year