Chainsaw-Team / ChainsawLinks
a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications
☆64Updated last year
Alternatives and similar repositories for Chainsaw
Users that are interested in Chainsaw are comparing it to the libraries listed below
Sorting:
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆50Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated last week
- ☆59Updated 2 years ago
- SDRAM controller with AXI4 interface☆96Updated 5 years ago
- General Purpose AXI Direct Memory Access☆55Updated last year
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago
- An AXI4 crossbar implementation in SystemVerilog☆164Updated last month
- RTL Verilog library for various DSP modules☆89Updated 3 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- ☆34Updated 6 years ago
- A Fast, Low-Overhead On-chip Network☆220Updated this week
- FFT generator using Chisel☆62Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆171Updated 8 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 4 years ago
- Network on Chip Implementation written in SytemVerilog☆186Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆138Updated 2 weeks ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 11 months ago
- ☆52Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆59Updated 5 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆88Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆66Updated 5 years ago
- ☆62Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated last week
- Vector processor for RISC-V vector ISA☆122Updated 4 years ago
- ☆23Updated 2 years ago