Chainsaw-Team / ChainsawLinks
a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications
☆67Updated last year
Alternatives and similar repositories for Chainsaw
Users that are interested in Chainsaw are comparing it to the libraries listed below
Sorting:
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆51Updated 2 years ago
- ☆66Updated 3 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated last week
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 2 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- A verilog implementation for Network-on-Chip☆78Updated 7 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆99Updated 5 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆196Updated 3 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated last week
- understanding of cocotb (In Chinese Only)☆20Updated 6 months ago
- ☆57Updated 6 years ago
- ☆39Updated 6 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- FFT generator using Chisel☆62Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆183Updated last year
- Vector processor for RISC-V vector ISA☆133Updated 5 years ago
- ☆23Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆255Updated last week
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated 3 weeks ago
- round robin arbiter☆77Updated 11 years ago