xjtuiair-cag / SiYuanLinks
A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS
☆31Updated 3 weeks ago
Alternatives and similar repositories for SiYuan
Users that are interested in SiYuan are comparing it to the libraries listed below
Sorting:
- ☆31Updated 5 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆29Updated this week
- ☆37Updated 7 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆43Updated 2 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- ☆56Updated 6 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆29Updated last month
- The official NaplesPU hardware code repository☆19Updated 6 years ago
- Original test vector of RISC-V Vector Extension☆14Updated 4 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆23Updated 2 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆54Updated 5 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆71Updated last year
- ☆22Updated 2 years ago
- ☆18Updated 2 years ago
- ☆31Updated 3 months ago
- ☆54Updated 6 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated last year
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Updated 6 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆30Updated 5 years ago
- systemc建模相关☆27Updated 11 years ago
- An almost empty chisel project as a starting point for hardware design☆33Updated 9 months ago
- Advanced Architecture Labs with CVA6☆70Updated last year
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Updated 9 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- ☆39Updated last year
- GPGPU supporting RISCV-V, developed with verilog HDL☆122Updated 8 months ago
- Pure digital components of a UCIe controller☆75Updated last week
- Administrative repository for the Integrated Matrix Extension Task Group☆29Updated 2 weeks ago