xjtuiair-cag / SiYuanLinks
A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS
☆33Updated 2 months ago
Alternatives and similar repositories for SiYuan
Users that are interested in SiYuan are comparing it to the libraries listed below
Sorting:
- ☆32Updated 4 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆44Updated 2 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- ☆57Updated 6 years ago
- ☆37Updated 7 years ago
- ☆31Updated 5 years ago
- HLS for Networks-on-Chip☆38Updated 4 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆30Updated this week
- ☆22Updated 2 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- The official NaplesPU hardware code repository☆20Updated 6 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆25Updated 3 months ago
- Original test vector of RISC-V Vector Extension☆14Updated 4 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Updated 9 years ago
- ☆19Updated 2 years ago
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆32Updated last year
- Advanced Architecture Labs with CVA6☆71Updated last year
- ☆30Updated 9 months ago
- ☆39Updated last year
- An almost empty chisel project as a starting point for hardware design☆33Updated 10 months ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆131Updated 10 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆31Updated last week
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- 自建 chisel 工程模板☆14Updated 2 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- ☆33Updated 9 months ago
- SystemC training aimed at TLM.☆34Updated 5 years ago
- CNN accelerator using NoC architecture☆17Updated 7 years ago