Alternatives and similar repositories for YunSuan:

Users that are interested in YunSuan are comparing it to the libraries listed below

• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆29Updated 3 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆67Updated 11 months ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆36Updated last week
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated this week
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆73Updated 3 weeks ago
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆15Updated last week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆57Updated 2 months ago
• sequencer / arithmetic
  ☆32Updated this week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆73Updated last month
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆53Updated last week
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆14Updated 7 months ago
• sifive / chisel-circt
  Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
  ☆70Updated last year
• pulp-platform / redmule
  ☆41Updated this week
• riscv / riscv-bfloat16
  ☆33Updated 6 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆42Updated last week
• riscv / riscv-test-env
  ☆43Updated last month
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆68Updated last week
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆161Updated last week
• chipsalliance / tilelink
  ☆27Updated last month
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆29Updated 3 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆99Updated 7 months ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 10 years ago
• ucb-bar / testchipip
  ☆82Updated 2 weeks ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated last year
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated last year
• HPC-Lab-IITB / Clarinet
  A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…
  ☆21Updated 2 years ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆26Updated 2 weeks ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆86Updated last week
• chipsalliance / diplomacy
  ☆18Updated 7 months ago