Alternatives and similar repositories for YunSuan

Users that are interested in YunSuan are comparing it to the libraries listed below

• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆126Updated 3 months ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆51Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆87Updated last year
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆92Updated last month
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆22Updated 11 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆36Updated 3 months ago
• chipsalliance / diplomacy
  ☆22Updated last month
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆99Updated 2 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆75Updated last week
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆70Updated last year
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆134Updated last month
• ucb-bar / radiance
  A Heterogeneous GPU Platform for Chipyard SoC
  ☆41Updated this week
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last month
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• ucb-bar / uciedigital
  An open-source UCIe controller implementation
  ☆81Updated this week
• OpenXiangShan / Utility
  ☆15Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆190Updated 3 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆75Updated last month
• pulp-platform / redmule
  ☆90Updated 2 weeks ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆163Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆62Updated 4 years ago
• OSCPU / chisel-playground
  ☆69Updated 11 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆184Updated last year
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆223Updated 2 months ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆114Updated 2 months ago
• openhwgroup / cv-hpdcache-verif
  Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
  ☆19Updated this week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 3 weeks ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆134Updated this week
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago