This repo includes XiangShan's function units
☆33Aug 29, 2026Updated this week
Alternatives and similar repositories for YunSuan
Users that are interested in YunSuan are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Scripts for XiangShan☆18Updated this week
- XiangShan Frontend Develop Environment☆72Updated this week
- ☆17Updated this week
- Open-source non-blocking L2 cache☆65Updated this week
- 简单的未优化的SRT除法器☆12Jun 16, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Modern co-simulation framework for RISC-V CPUs☆182Updated this week
- Open source high performance IEEE-754 floating unit☆99Feb 26, 2024Updated 2 years ago
- 给NEMU移植Linux Kernel!☆23Jun 1, 2025Updated last year
- This project records the process of optimizing SGEMM (single-precision floating point General Matrix Multiplication) on the riscv platfor…☆24Dec 11, 2024Updated last year
- ☆15Jul 18, 2026Updated last month
- ☆50May 11, 2022Updated 4 years ago
- Documentation for XiangShan☆445Aug 19, 2026Updated last week
- Wrapper for ETH Ariane Core☆21Sep 2, 2025Updated 11 months ago
- Documentation for XiangShan Design☆51Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- The Unified TileLink Memory Subsystem Tester for XiangShan☆15Updated this week
- A library to retrieve JEP106 manufacturer strings in Rust.☆12May 7, 2025Updated last year
- Unit tests generator for RVV 1.0☆116May 25, 2026Updated 3 months ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆41Feb 6, 2024Updated 2 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆56Aug 14, 2024Updated 2 years ago
- GEMM and GEMM-Ops accelerator for PULP systems☆115Aug 5, 2026Updated 3 weeks ago
- ☆10Oct 15, 2021Updated 4 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆35Apr 13, 2025Updated last year
- Nix template for the chisel-based industrial designing flows.☆58Jul 21, 2026Updated last month
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Build mini linux for your own RISC-V emulator!☆25Sep 11, 2024Updated last year
- Open-source high-performance non-blocking cache☆101Jun 17, 2026Updated 2 months ago
- Equivalence checking with Yosys☆61Aug 5, 2026Updated 3 weeks ago
- A Library of Chisel3 Tools for Digital Signal Processing☆250Apr 29, 2024Updated 2 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆46Apr 2, 2025Updated last year
- An RTL generator for a last-level shared inclusive TileLink cache controller☆25Aug 8, 2026Updated 3 weeks ago
- ☆156Updated this week
- ☆11Jan 9, 2021Updated 5 years ago
- SpacemiT K3 X100 A100 - random snippets from this RISC-V CPU☆23May 18, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- Generate Linux Perf event tables for Apple Silicon☆19Dec 16, 2025Updated 8 months ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Reasoning LLMs optimized for Chisel code generation☆26Jun 19, 2025Updated last year
- 6-stage dual-issue in-order superscalar risc-v cpu☆15Updated this week
- ☆17Feb 5, 2026Updated 6 months ago
- Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS☆17Jul 3, 2026Updated last month