Alternatives and similar repositories for YunSuan

Users that are interested in YunSuan are comparing it to the libraries listed below

• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆50Updated this week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆86Updated last year
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆121Updated last month
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆189Updated 6 months ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆36Updated last month
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆22Updated 10 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆91Updated 3 weeks ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆95Updated 2 weeks ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆73Updated 2 weeks ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆182Updated last year
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆68Updated last year
• pulp-platform / redmule
  ☆88Updated this week
• OpenXiangShan / Utility
  ☆15Updated this week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆124Updated last week
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆111Updated 2 weeks ago
• OSCPU / chisel-playground
  ☆68Updated 9 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆190Updated 2 weeks ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆187Updated 2 months ago
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆45Updated last week
• ucb-bar / uciedigital
  An open-source UCIe controller implementation
  ☆76Updated last week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆222Updated 3 weeks ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆93Updated 3 weeks ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆130Updated 5 years ago
• chipsalliance / diplomacy
  ☆21Updated 8 months ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆107Updated 3 months ago
• ucb-bar / radiance
  A Heterogeneous GPU Platform for Chipyard SoC
  ☆39Updated this week
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆157Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆71Updated last year