OpenXiangShan / YunSuanLinks
This repo includes XiangShan's function units
☆27Updated this week
Alternatives and similar repositories for YunSuan
Users that are interested in YunSuan are comparing it to the libraries listed below
Sorting:
- Chisel RISC-V Vector 1.0 Implementation☆111Updated 3 weeks ago
- Open-source non-blocking L2 cache☆49Updated this week
- Open source high performance IEEE-754 floating unit☆84Updated last year
- Vector Acceleration IP core for RISC-V*☆183Updated 4 months ago
- Open-source high-performance non-blocking cache☆89Updated last week
- An RTL generator for a last-level shared inclusive TileLink cache controller☆22Updated 8 months ago
- A Rocket-based RISC-V superscalar in-order core☆35Updated 4 months ago
- Unit tests generator for RVV 1.0☆92Updated this week
- Pick your favorite language to verify your chip.☆68Updated last week
- ☆67Updated 7 months ago
- ☆76Updated last week
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆42Updated this week
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆118Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆210Updated last month
- For contributions of Chisel IP to the chisel community.☆65Updated 10 months ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆155Updated last year
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆23Updated this week
- chipyard in mill :P☆78Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- Advanced Architecture Labs with CVA6☆68Updated last year
- ☆14Updated this week
- Chisel Learning Journey☆110Updated 2 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆102Updated last week
- Modern co-simulation framework for RISC-V CPUs☆157Updated this week
- An energy-efficient RISC-V floating-point compute cluster.☆109Updated this week
- ☆86Updated 3 months ago
- ☆21Updated 6 months ago