Reasoning LLMs optimized for Chisel code generation
☆23Jun 19, 2025Updated 8 months ago
Alternatives and similar repositories for ChiseLLM
Users that are interested in ChiseLLM are comparing it to the libraries listed below
Sorting:
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- ☆19Jul 12, 2024Updated last year
- Build mini linux for your own RISC-V emulator!☆24Sep 11, 2024Updated last year
- ☆13Feb 14, 2026Updated 2 weeks ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆18Feb 3, 2026Updated 3 weeks ago
- ☆10Oct 15, 2021Updated 4 years ago
- RISC-V Formal in Chisel☆12Apr 9, 2024Updated last year
- Formal verification tools for Chisel and RISC-V☆13Jul 2, 2024Updated last year
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- 本项目已被合并至官方Chiplab中☆13Jan 13, 2025Updated last year
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆31Feb 10, 2020Updated 6 years ago
- ☆33Aug 7, 2025Updated 6 months ago
- The 'missing header' for Chisel☆23Feb 5, 2026Updated 3 weeks ago
- QuardStar Tutorial is all you need !☆17Sep 11, 2024Updated last year
- ☆21May 26, 2025Updated 9 months ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Sep 4, 2025Updated 5 months ago
- Fuzzing General-Purpose Hardware Designs with Software Fuzzers☆24Jan 11, 2026Updated last month
- ☆17Jul 11, 2021Updated 4 years ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated 11 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆24Jan 21, 2026Updated last month
- Generative Benchmark for LLM-Aided Hardware Design☆27Jun 4, 2025Updated 8 months ago
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛(龙芯杯)团队赛二等奖作品☆23Sep 14, 2024Updated last year
- Equivalence checking with Yosys☆58Updated this week
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆25Jan 25, 2026Updated last month
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆26Jan 2, 2025Updated last year
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆57Oct 27, 2024Updated last year
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- ☆36Jul 22, 2025Updated 7 months ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆28Dec 18, 2024Updated last year
- Fuzz everything! Now let's fuzz chip!☆34Feb 11, 2026Updated 2 weeks ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Feb 25, 2025Updated last year
- Local test cases for SysY compilers, used by compiler-dev.☆28Mar 5, 2022Updated 3 years ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆30Mar 13, 2024Updated last year
- Documentation for XiangShan Design☆42Feb 3, 2026Updated 3 weeks ago
- Fix syntax errors of LLM-generated RTL☆43May 23, 2024Updated last year
- ☆71Feb 2, 2026Updated 3 weeks ago
- SUSTech CS202 (Computer Organization) Project, with CPU hardware implemented in Chisel(Scala) and software cross-compiled from Rust.☆34Jun 16, 2023Updated 2 years ago
- Kendryte K210 SBI support using RustSBI, provides privileged spec 1.12 environment by emulating it using 1.9.1☆37Feb 18, 2024Updated 2 years ago