Alternatives and similar repositories for apple-pmu

Users that are interested in apple-pmu are comparing it to the libraries listed below

• cyyself / m1-pmu-gen
  Generate Linux Perf event tables for Apple Silicon
  ☆14Updated 2 weeks ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• efeslab / moesi-prime
  ☆15Updated 2 years ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 3 years ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆65Updated 2 weeks ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆43Updated last month
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆20Updated 11 months ago
• trivialmips / linux-nontrivial-mips
  Linux porting to NonTrivialMIPS (based on linux-stable)
  ☆12Updated 6 years ago
• comparch-security / chipyard-random-llc
  A Rocket-Chip with a Dynamically Randomized LLC
  ☆13Updated last year
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆23Updated 8 months ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 4 years ago
• atrosinenko / memtest86-plus-riscv
  Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)
  ☆16Updated 5 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 3 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆35Updated last year
• jiegec / kb
  My knowledge base
  ☆72Updated last week
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated 2 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 3 weeks ago
• iscas-tis / ChiRVFormal
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆15Updated 5 months ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆10Updated 3 years ago
• bakhi / GPUReplay
  GPUReplay, ASPLOS 2022
  ☆41Updated 3 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• dtcxzyw / static-key
  Header-only C/C++ static keys to avoid the overhead of conditional branches
  ☆14Updated last year
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆24Updated this week
• aakahlow / gem5Valid_Haswell
  ☆20Updated 5 years ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆14Updated 3 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• nus-comparch / looppoint
  Sampled simulation of multi-threaded applications using LoopPoint methodology
  ☆23Updated 3 months ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 2 years ago