Alternatives and similar repositories for OpenLLC

Users that are interested in OpenLLC are comparing it to the libraries listed below

• carlosedp / riscvassembler
  A RISC-V assembler library for Scala/Chisel HDL projects
  ☆16Updated 3 weeks ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 8 months ago
• OpenXiangShan / Utility
  ☆15Updated last week
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆50Updated this week
• chipsalliance / rocket-chip-inclusive-cache
  An RTL generator for a last-level shared inclusive TileLink cache controller
  ☆22Updated 10 months ago
• chipsalliance / cde
  A Scala library for Context-Dependent Environments
  ☆49Updated last year
• ucb-bar / cva6-wrapper
  Wrapper for ETH Ariane Core
  ☆21Updated 3 months ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆92Updated this week
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆28Updated 2 weeks ago
• Chlorophytus / broccoli
  A soft multimedia/graphics processor prototype in Chisel 3
  ☆11Updated 2 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆36Updated last week
• ducky64 / chisualizer
  Block-diagram style digital logic visualizer
  ☆23Updated 10 years ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆91Updated last week
• firesim / icenet
  Network components (NIC, Switch) for FireBox
  ☆19Updated last year
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆86Updated last year
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• ucb-bar / testchipip
  ☆87Updated this week
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated last year
• IntelLabs / riscv-vector
  Vector Acceleration IP core for RISC-V*
  ☆190Updated 7 months ago
• chipsalliance / diplomacy
  ☆22Updated last week
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆36Updated 2 months ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆39Updated 4 months ago
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆49Updated 2 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated last week
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆159Updated last year
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆105Updated 3 weeks ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆59Updated 2 years ago
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆20Updated last year
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆59Updated this week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆117Updated 3 years ago