Zhao-Dongyu / sgemm_riscv
This project records the process of optimizing SGEMM (single-precision floating point General Matrix Multiplication) on the riscv platform.
☆16Updated 8 months ago
Related projects ⓘ
Alternatives and complementary repositories for sgemm_riscv
- ☆30Updated 4 months ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Updated 3 years ago
- HeteroCL-MLIR dialect for accelerator design☆40Updated last month
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆19Updated 3 months ago
- A polyhedral compiler for hardware accelerators☆56Updated 3 months ago
- Chisel RISC-V Vector 1.0 Implementation☆50Updated this week
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆86Updated this week
- TVM for chips base on Xuantie CPU, an open deep learning compiler stack.☆30Updated 4 months ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆22Updated this week
- Floating point modules for CHISEL☆28Updated 10 years ago
- The translator that supports translating NVPTX to SPIR-V. This translator is modified from LLVM-SPIR-V Translator.☆33Updated 3 years ago
- LLVM OpenCL C compiler suite for ventus GPGPU☆32Updated this week
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆16Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆59Updated 10 months ago
- ☆21Updated last month
- IREE plugin repository for the AMD AIE accelerator☆66Updated this week
- RiVEC Bencmark Suite☆104Updated this week
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆52Updated this week
- upstream: https://github.com/RALC88/gem5☆32Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆36Updated last month
- ☆84Updated 8 months ago
- A hardware synthesis framework with multi-level paradigm☆35Updated last year
- agile hardware-software co-design☆44Updated 2 years ago
- Polyhedral High-Level Synthesis in MLIR☆29Updated last year
- ETHZ Heterogeneous Accelerated Compute Cluster.☆29Updated last month
- ☆79Updated this week
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆62Updated last week
- A OpenCL-based FPGA benchmark suite for HPC☆33Updated last week
- Ventus GPGPU ISA Simulator Based on Spike☆37Updated last week
- A hardware design framework with a timing-deterministic, Rust-embedded HDL and the compilation flow.☆12Updated 7 months ago