Simple library for decoding RISC-V instructions
☆24Nov 19, 2025Updated 6 months ago
Alternatives and similar repositories for riscv-decode
Users that are interested in riscv-decode are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Rocket-based RISC-V superscalar in-order core☆39Mar 11, 2026Updated 2 months ago
- Hypervisor written in Rust for the RISC-V 1.0 hypervisor extension☆16Oct 21, 2024Updated last year
- ☆11Jun 9, 2022Updated 3 years ago
- Computer architecture learning environment using FPGAs☆15May 17, 2021Updated 5 years ago
- ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)☆25May 11, 2026Updated 2 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Low level access to RISCV processors☆22Oct 3, 2022Updated 3 years ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆20Apr 14, 2026Updated last month
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated 2 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆28Jul 17, 2025Updated 10 months ago
- Minimal ncurses implementation for use in embedded environments☆12Oct 29, 2017Updated 8 years ago
- Let's write an OS which can run on ARM in Rust from scratch! (🚧WIP)☆18Mar 13, 2022Updated 4 years ago
- Paging Debug tool for GDB using python☆13Jun 4, 2022Updated 3 years ago
- Intel AMT Serial-Over-LAN (SOL) client☆13Feb 23, 2024Updated 2 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- NOVA Microhypervisor☆11May 12, 2026Updated last week
- 6-stage dual-issue in-order superscalar risc-v cpu☆14May 2, 2026Updated 3 weeks ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆34Apr 13, 2025Updated last year
- Run Rocket Chip on VCU128☆30Oct 21, 2025Updated 7 months ago
- Rust crate for numpy NPY files☆33May 3, 2026Updated 3 weeks ago
- ☆14Feb 24, 2025Updated last year
- The Verilog source code for DRUM approximate multiplier.☆32May 4, 2023Updated 3 years ago
- Linux kernel source tree☆14Jun 25, 2025Updated 11 months ago
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implementing the Precise Runahead (HPCA'20) in gem5☆14Oct 5, 2023Updated 2 years ago
- 🦜 yair - a high-level compiler IR entirely written in Rust☆37Dec 11, 2021Updated 4 years ago
- Supporting code for "LLMs for your iPhone: Whole-Tensor 4 Bit Quantization"☆11Mar 31, 2024Updated 2 years ago
- hvisor tool for root linux, includes CLI, Virtio daemon and hvisor kernel module☆15Updated this week
- This repo includes XiangShan's function units☆30May 1, 2026Updated 3 weeks ago
- A repository that helps to convert the YOLOv8 detection model to OpenVINO format via onnx and make it more optimized with int8 quantizati…☆12Mar 12, 2023Updated 3 years ago
- note about IC knowledge☆10Sep 7, 2022Updated 3 years ago
- HyperBench: A Benchmark Suite for Virtualization Capabilities☆31Nov 22, 2019Updated 6 years ago
- ☆18Jul 12, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)☆11Jul 29, 2020Updated 5 years ago
- ☆13Nov 27, 2025Updated 5 months ago
- ☆17Apr 30, 2025Updated last year
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Aug 18, 2022Updated 3 years ago
- For CPU experiment☆14Feb 23, 2021Updated 5 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 8 years ago
- Graph model execution API for Candle☆17Jul 27, 2025Updated 9 months ago