Alternatives and similar repositories for riscv-decode:

Users that are interested in riscv-decode are comparing it to the libraries listed below

• nbdd0121 / r2vm
  Rust RISC-V Virtual Machine
  ☆91Updated 2 months ago
• GregAC / rrs
  Rust RISC-V Simulator
  ☆28Updated 9 months ago
• djg / verilated-rs
  Verilator Porcelain
  ☆42Updated last year
• rvkrypto / rvkrypto-fips
  [HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension
  ☆26Updated 6 months ago
• elliottt / easy-smt
  Easy SMT solver interaction
  ☆30Updated this week
• stephank / rvsim
  A RISC-V simulator implementing RV32G[C].
  ☆34Updated last year
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆30Updated 3 months ago
• sbates130272 / docker-riscv
  A Dockerfile for the tools needed to develop for the RISC-V open-source CPU
  ☆25Updated 6 years ago
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 4 years ago
• eigenraven / rvasm
  RISC-V Assembler
  ☆18Updated last year
• mark-i-m / os2
  x86_64 OS kernel with completely async userspace and single address space [WIP; but basic kernel functionality implemented]
  ☆31Updated 4 years ago
• jjyr / buddy-alloc
  Buddy-alloc is a memory allocator for no-std Rust, used for embedded environments.
  ☆28Updated 2 months ago
• Amanieu / mini-backtrace
  Backtrace support for Rust `no_std` and embedded programs.
  ☆48Updated last year
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆43Updated this week
• jwnhy / rvbt
  Baremetal Backtracing on RISC-V
  ☆15Updated 3 years ago
• rems-project / isla
  Symbolic execution tool for Sail ISA specifications
  ☆64Updated 2 weeks ago
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆30Updated last week
• stefanpie / sa-placer
  ☆14Updated 11 months ago
• Amanieu / a-tale-of-binary-translation
  Simple RISC-V emulator presented at Rust Nation 2023
  ☆61Updated last year
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆37Updated 3 months ago
• shady831213 / terminus
  A riscv isa simulator in rust.
  ☆63Updated last year
• tcr / rust-verilog
  Verilog parsing and generator crate.
  ☆20Updated 4 years ago
• DrChat / buddyalloc
  Buddy allocator, forked from the toyos repository.
  ☆14Updated 3 years ago
• calyxir / calyx-riscv
  RISCV Core written in Calyx
  ☆15Updated 5 months ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 2 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆56Updated this week
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆74Updated this week
• djanderson / riscv-5stage-simulator
  A 5-stage pipelining RISC-V 32I simulator written in Rust.
  ☆19Updated 3 years ago
• litex-hub / pythondata-cpu-rocket
  Python module containing verilog files for rocket cpu (for use with LiteX).
  ☆13Updated 3 weeks ago
• lowRISC / manticore
  ☆16Updated 2 years ago