Alternatives and similar repositories for toffee

Users that are interested in toffee are comparing it to the libraries listed below

• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆77Updated last week
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆46Updated 2 months ago
• XS-MLVP / Example-NutShellCache
  开放验证平台NutShell Cache验证案例
  ☆11Updated 2 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• OSCPU / chisel-playground
  ☆71Updated last week
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆171Updated this week
• OSCPU / yosys-sta
  ☆90Updated 3 months ago
• OSCPU / ysyxSoC
  ☆92Updated 4 months ago
• OpenXiangShan / gsim
  ☆65Updated last month
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆42Updated last week
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆223Updated last week
• Jpz-sdju / trinity
  ☆32Updated 6 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆160Updated last year
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆33Updated last week
• XS-MLVP / UCAgent
  UnityChip Verification AI-Agent
  ☆91Updated this week
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆62Updated 4 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆77Updated 2 years ago
• pku-liang / ksim
  ☆52Updated last year
• OpenXiangShan / GEM5
  ☆125Updated last week
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆25Updated last year
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆45Updated last year
• openhwgroup / cv-hpdcache-verif
  Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
  ☆20Updated last month
• pkuzjx / EDA-wiki
  EDA wiki
  ☆136Updated 3 months ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆77Updated 2 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 2 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆32Updated 9 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated this week
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆226Updated 3 months ago
• CherrySprings / CherrySprings
  ☆19Updated 2 years ago