Alternatives and similar repositories for toffee

Users that are interested in toffee are comparing it to the libraries listed below

• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆51Updated this week
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆35Updated last week
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆27Updated last month
• OSCPU / chisel-playground
  ☆68Updated 4 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 2 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• OSCPU / ysyxSoC
  ☆86Updated last month
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 10 months ago
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated 2 weeks ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 7 months ago
• puckbee / moli
  ☆15Updated last week
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 3 months ago
• XS-MLVP / env-xs-ov-00-bpu
  香山微架构开放验证第一期：昆明湖BPU模块UT测试模块及环境
  ☆29Updated 8 months ago
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 9 months ago
• Jpz-sdju / trinity
  ☆24Updated 2 months ago
• isnthzy / lightsss-chiplab
  本项目已被合并至官方Chiplab中
  ☆12Updated 5 months ago
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆18Updated 3 weeks ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆19Updated last month
• OpenXiangShan / GEM5
  ☆88Updated this week
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 2 months ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆55Updated 10 months ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆62Updated last year
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆19Updated last month
• jaypiper / simulator
  ☆31Updated 2 weeks ago