XS-MLVP / toffee
A framework for building hardware verification platform using software method
☆17Updated 2 weeks ago
Alternatives and similar repositories for toffee:
Users that are interested in toffee are comparing it to the libraries listed below
- Pick your favorite language to verify your chip.☆47Updated this week
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆29Updated this week
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated last week
- ☆85Updated 2 months ago
- "aura" my super-scalar O3 cpu core☆24Updated 11 months ago
- ☆63Updated this week
- Documentation for XiangShan Design☆23Updated this week
- ☆21Updated 3 weeks ago
- ☆66Updated 8 months ago
- 香山微架构开放验证第一期:昆明湖BPU模块UT测试模块及环境☆26Updated 6 months ago
- ☆64Updated 2 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆50Updated 2 years ago
- Basic chisel difftest environment for RTL design (WIP☆18Updated last month
- Build mini linux for your own RISC-V emulator!☆19Updated 7 months ago
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆16Updated 3 months ago
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated last year
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆48Updated 5 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆153Updated 6 months ago
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆19Updated 5 months ago
- Modern co-simulation framework for RISC-V CPUs☆139Updated this week
- ☆80Updated this week
- ☆18Updated last year
- ☆64Updated 2 years ago
- ☆27Updated this week
- ☆41Updated 2 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 5 years ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆11Updated 3 weeks ago
- A framework for ysyx flow☆11Updated 5 months ago
- ☆22Updated 2 years ago