Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
☆27Mar 1, 2021Updated 5 years ago
Alternatives and similar repositories for sphinx-verilog-domain
Users that are interested in sphinx-verilog-domain are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- APB Logic☆26May 16, 2026Updated last month
- ☆40Jun 13, 2015Updated 11 years ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago
- Reflection API for SystemVerilog☆14Mar 30, 2026Updated 2 months ago
- ☆13Aug 22, 2022Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Doxygen with verilog support☆41Mar 15, 2019Updated 7 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Dec 30, 2022Updated 3 years ago
- Solving Sudokus using open source formal verification tools☆18Aug 16, 2022Updated 3 years ago
- A sphinx extension that allows including wavedrom diagrams by using its text-based representation☆39Sep 3, 2024Updated last year
- This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol☆14Jul 11, 2018Updated 7 years ago
- A collection of core generators to use with FuseSoC☆18Aug 23, 2024Updated last year
- IP-XACT XML binding library☆16Jun 23, 2016Updated 9 years ago
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 9 years ago
- ☆30Sep 3, 2025Updated 9 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Running Python code in SystemVerilog☆73May 8, 2026Updated last month
- My local copy of UVM-SystemC☆14Apr 27, 2024Updated 2 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆52Jan 13, 2021Updated 5 years ago
- ☆15May 10, 2019Updated 7 years ago
- ☆27Mar 17, 2026Updated 3 months ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Dec 26, 2023Updated 2 years ago
- Scripts for XiangShan☆17Updated this week
- Tools for SystemVerilog development.☆15Jan 3, 2018Updated 8 years ago
- Tool to fetch and parse data about Efabless MPW projects☆15Jan 10, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- GitLab runner for HPC systems using ENROOT and SLURM☆33Sep 28, 2023Updated 2 years ago
- An Emacs minor mode that highlights current word in all visible buffers☆13Jan 7, 2024Updated 2 years ago
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- Contains reference architecture scripts for running the OpenPiton regression using auto-scaling SLURM cluster.☆22Feb 25, 2026Updated 3 months ago
- ☆16May 6, 2026Updated last month
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆20Apr 27, 2024Updated 2 years ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- ☆43May 26, 2018Updated 8 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆19Nov 23, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 7 months ago
- Generates a SystemVerilog assertion interface for a given SV RTL design☆20Mar 23, 2025Updated last year
- Python interface for cross-calling with HDL☆51Mar 14, 2026Updated 3 months ago
- Python library for the SDS011 Air Quality Sensor☆12Dec 16, 2023Updated 2 years ago
- Simple UVM environment for experimenting with Verilator.☆39Apr 29, 2026Updated last month
- Connecting SystemC with SystemVerilog☆43Mar 25, 2012Updated 14 years ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆65Jan 28, 2026Updated 4 months ago