Alternatives and similar repositories for sphinx-verilog-domain:

Users that are interested in sphinx-verilog-domain are comparing it to the libraries listed below

• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆30Updated this week
• blockwork-eda / blockwork
  An opinionated build environment for EDA projects
  ☆15Updated this week
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆22Updated 3 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆29Updated last month
• mtdsousa / antlr4-verilog-python
  Generated files from ANTLR4 for Verilog parsing in Python
  ☆12Updated 2 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆33Updated 4 months ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆57Updated 7 months ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆22Updated 4 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 5 years ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆27Updated last month
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆16Updated 9 months ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆15Updated 8 years ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆12Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 5 months ago
• svunit / svmock
  A mock framework for use with SVUnit
  ☆15Updated last year
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆47Updated 8 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 11 months ago
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated 2 months ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆37Updated 4 years ago
• antmicro / verilator-verification-features-tests
  ☆17Updated this week
• amiq-consulting / uvm_reg_to_ipxact
  ☆15Updated 5 years ago
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆36Updated 9 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated 2 months ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆9Updated 4 years ago
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆33Updated 10 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated 2 years ago
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated 2 weeks ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 3 years ago
• wallento / cocotbext-wishbone
  ☆13Updated 2 months ago
• amiq-consulting / cagt
  Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …
  ☆12Updated 9 years ago