Alternatives and similar repositories for XiangShan-Design-Doc

Users that are interested in XiangShan-Design-Doc are comparing it to the libraries listed below

• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 4 months ago
• OSCPU / yosys-sta
  ☆78Updated 4 months ago
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 11 months ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆20Updated 3 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆64Updated last week
• OSCPU / chisel-playground
  ☆67Updated 6 months ago
• OpenXiangShan / gsim
  ☆52Updated last week
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• XS-MLVP / toffee
  A framework for building hardware verification platform using software method
  ☆25Updated 2 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆178Updated 10 months ago
• OSCPU / ysyxSoC
  ☆86Updated last week
• puckbee / moli
  ☆28Updated last month
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆38Updated this week
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 9 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆148Updated last week
• OpenXiangShan / GEM5
  ☆97Updated this week
• Jpz-sdju / trinity
  ☆25Updated 3 weeks ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆65Updated last year
• isnthzy / lightsss-chiplab
  本项目已被合并至官方Chiplab中
  ☆12Updated 7 months ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 5 months ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆83Updated last year
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆18Updated 2 months ago
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated 2 months ago
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 2 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆206Updated 2 months ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 3 months ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆25Updated 3 months ago