Alternatives and similar repositories for XiangShan-Design-Doc

Users that are interested in XiangShan-Design-Doc are comparing it to the libraries listed below

• ysyx-ta / ysyx-summer-readings
  ☆66Updated 11 months ago
• OSCPU / yosys-sta
  ☆73Updated 2 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆172Updated 9 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 3 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆51Updated this week
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 10 months ago
• OSCPU / ysyxSoC
  ☆86Updated 2 months ago
• OSCPU / chisel-playground
  ☆67Updated 5 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• OpenXiangShan / gsim
  ☆39Updated this week
• puckbee / moli
  ☆15Updated last week
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆35Updated this week
• OpenXiangShan / GEM5
  ☆89Updated this week
• yizishun / ysyx-framework
  A framework for ysyx flow
  ☆11Updated 8 months ago
• NoAXI / NoAXI-LoongArch-CPU
  Second Prize in NSCSCC 2024. Developed by team NoAXI from Hangzhou Dianzi University.
  ☆17Updated 10 months ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆21Updated 4 months ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 3 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆147Updated this week
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆65Updated last year
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 8 months ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated last month
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 2 years ago
• XS-MLVP / toffee
  A framework for building hardware verification platform using software method
  ☆20Updated last month
• ysyx-ta / ysyx-slides
  ☆30Updated 3 weeks ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 4 months ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆19Updated 2 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆204Updated last month
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago