Alternatives and similar repositories for XiangShan-Design-Doc

Users that are interested in XiangShan-Design-Doc are comparing it to the libraries listed below

• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆50Updated last week
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 10 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 2 months ago
• OSCPU / chisel-playground
  ☆68Updated 4 months ago
• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆35Updated last week
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 7 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• puckbee / moli
  ☆15Updated last week
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 9 months ago
• XS-MLVP / toffee
  A framework for building hardware verification platform using software method
  ☆20Updated 3 weeks ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• Jpz-sdju / trinity
  ☆24Updated 2 months ago
• jaypiper / simulator
  ☆31Updated last week
• NoAXI / NoAXI-LoongArch-CPU
  Second Prize in NSCSCC 2024. Developed by team NoAXI from Hangzhou Dianzi University.
  ☆17Updated 9 months ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 2 months ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆21Updated 4 months ago
• OpenXiangShan / GEM5
  ☆86Updated this week
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆19Updated last month
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆18Updated 3 weeks ago
• XS-MLVP / env-xs-ov-00-bpu
  香山微架构开放验证第一期：昆明湖BPU模块UT测试模块及环境
  ☆29Updated 8 months ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• Tanggling / BOOMCore
  This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…
  ☆16Updated 8 months ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 3 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆171Updated 8 months ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆18Updated last month
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated last week