Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
☆56Aug 14, 2024Updated 2 years ago
Alternatives and similar repositories for nano-cpu32k
Users that are interested in nano-cpu32k are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆31Aug 8, 2020Updated 6 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 4 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆17Sep 18, 2026Updated last month
- ☆20May 1, 2023Updated 3 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆41Feb 6, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆16Jul 16, 2026Updated 3 months ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- The official NaplesPU hardware code repository☆37Jul 27, 2019Updated 7 years ago
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- A Verilog implementation of a processor cache.☆40Dec 29, 2017Updated 8 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆39Oct 27, 2026Updated last week
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Feb 17, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Tensor computing core☆15Jul 8, 2026Updated 3 months ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- Design a cache by using Verilog☆13Jan 12, 2017Updated 9 years ago
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆19Updated this week
- FPGA Many-core Processor Implementation☆11Nov 27, 2024Updated last year
- ☆10Dec 15, 2023Updated 2 years ago
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆47Updated this week
- AXI Interconnect☆59Aug 20, 2021Updated 5 years ago
- A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs☆11Jun 19, 2020Updated 6 years ago
- ☆13Oct 11, 2023Updated 3 years ago
- SoC Based on ARM Cortex-M3☆40May 16, 2025Updated last year
- SoC based on RISC V ISA☆10Apr 22, 2022Updated 4 years ago
- Synthesizable and Parameterized Cache Controller in Verilog☆49Jun 13, 2023Updated 3 years ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆16Dec 4, 2025Updated 11 months ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- 128KB AXI cache (32-bit in, 256-bit out)☆58May 10, 2021Updated 5 years ago
- ☆44Jul 28, 2025Updated last year
- ☆15Oct 27, 2026Updated last week
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated this week
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 4 years ago
- ☆79Apr 23, 2023Updated 3 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated 2 years ago