Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
☆55Aug 14, 2024Updated last year
Alternatives and similar repositories for nano-cpu32k
Users that are interested in nano-cpu32k are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆31Aug 8, 2020Updated 5 years ago
- ☆14Feb 24, 2025Updated last year
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆13Mar 30, 2023Updated 2 years ago
- A Verilog implementation of a processor cache.☆37Dec 29, 2017Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- ☆34Jul 28, 2025Updated 7 months ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆37Oct 23, 2025Updated 5 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- UVM testbench for verifying the Pulpino SoC