Alternatives and similar repositories for nano-cpu32k

Users that are interested in nano-cpu32k are comparing it to the libraries listed below

• ljgibbslf / basic_cache_core
  ☆29Updated 5 years ago
• pulp-platform / fpu
  ☆53Updated 6 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆66Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆41Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆57Updated last year
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated last week
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆65Updated last year
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆19Updated 5 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆169Updated this week
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆60Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆34Updated 6 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆53Updated 4 years ago
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated last month
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆52Updated 5 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆44Updated last year
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 10 months ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• oprecomp / DDR4_controller
  ☆64Updated 4 years ago
• hyf6661669 / verilog_library
  HYF's high quality verilog codes
  ☆15Updated 8 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆50Updated 7 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated this week
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆76Updated 7 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆126Updated 4 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆30Updated 2 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆46Updated 3 years ago