Pick your favorite language to verify your chip.
☆79Jan 30, 2026Updated last month
Alternatives and similar repositories for picker
Users that are interested in picker are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A framework for building hardware verification platform using software method☆33Dec 24, 2025Updated 2 months ago
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆46Feb 25, 2026Updated 3 weeks ago
- 开放验证平台NutShell Cache验证案例☆11Dec 2, 2025Updated 3 months ago
- ☆67Mar 3, 2026Updated 2 weeks ago
- ☆13Mar 15, 2026Updated last week
- 香山微架构开放验证第一期：昆明湖BPU模块UT测试模块及环境☆30Oct 20, 2024Updated last year
- Xiangshan deterministic workloads generator☆24May 14, 2025Updated 10 months ago
- Build mini linux for your own RISC-V emulator!☆24Sep 11, 2024Updated last year
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- UCAS SEP扩展脚本 - 课程评估辅助 etc.☆12Apr 3, 2025Updated 11 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆40Apr 3, 2025Updated 11 months ago
- Qemu tracing plugin using SimPoints☆17Sep 12, 2024Updated last year
- The Scala parser to parse riscv/riscv-opcodes generate☆25Jan 21, 2026Updated 2 months ago
- high-performance RTL simulator☆188Jun 19, 2024Updated last year
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- ☆16Updated this week
- ☆19Jan 2, 2026Updated 2 months ago
- Generate Linux Perf event tables for Apple Silicon☆17Dec 16, 2025Updated 3 months ago
- 计算机体系结构基础 第二版 个人答案☆13Jun 10, 2021Updated 4 years ago
- Open-source AI acceleration on FPGA: from ONNX to RTL☆49Updated this week
- ☆97Mar 5, 2026Updated 2 weeks ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆30Oct 7, 2024Updated last year
- ☆43Mar 31, 2025Updated 11 months ago
- ☆13Jan 20, 2023Updated 3 years ago
- This repo includes XiangShan's function units☆30Feb 14, 2026Updated last month
- RISC-V Matrix Specification☆23Dec 2, 2024Updated last year
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Oct 9, 2021Updated 4 years ago
- Modern co-simulation framework for RISC-V CPUs☆172Mar 16, 2026Updated last week
- ☆12Mar 12, 2026Updated last week
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 4 months ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- ☆81Oct 29, 2024Updated last year
- ☆64Dec 4, 2022Updated 3 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆202Oct 14, 2024Updated last year
- ☆17Mar 26, 2025Updated 11 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆36Jan 16, 2025Updated last year
- 本项目已被合并至官方Chiplab中☆13Jan 13, 2025Updated last year
- Recent papers related to hardware formal verification.☆77Sep 20, 2023Updated 2 years ago