Alternatives and similar repositories for picker

Users that are interested in picker are comparing it to the libraries listed below

• XS-MLVP / toffee
  A framework for building hardware verification platform using software method
  ☆28Updated last month
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆42Updated last week
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆52Updated 3 years ago
• OSCPU / yosys-sta
  ☆83Updated 5 months ago
• OpenXiangShan / GEM5
  ☆103Updated this week
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆157Updated this week
• OSCPU / chisel-playground
  ☆67Updated 7 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆32Updated this week
• OSCPU / ysyxSoC
  ☆87Updated this week
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 5 months ago
• OpenXiangShan / gsim
  ☆55Updated last month
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆66Updated last week
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆210Updated 4 months ago
• Jpz-sdju / trinity
  ☆28Updated 2 months ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆30Updated 3 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆68Updated last year
• sequencer / arithmetic
  ☆33Updated 6 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆89Updated 2 weeks ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆76Updated 2 weeks ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆84Updated last year
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆211Updated last month
• openhwgroup / cv-hpdcache-verif
  Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
  ☆18Updated 7 months ago