Alternatives and similar repositories for picker

Users that are interested in picker are comparing it to the libraries listed below

• XS-MLVP / toffee
  A framework for building hardware verification platform using software method
  ☆32Updated last month
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆46Updated 2 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆170Updated this week
• OSCPU / yosys-sta
  ☆90Updated 2 months ago
• OSCPU / ysyxSoC
  ☆92Updated 3 months ago
• OpenXiangShan / GEM5
  ☆123Updated this week
• OSCPU / chisel-playground
  ☆70Updated 11 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆25Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated this week
• CherrySprings / CherrySprings
  ☆19Updated 2 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆32Updated 9 months ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆40Updated last week
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆89Updated last year
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆220Updated 2 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆100Updated 2 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• XS-MLVP / Example-NutShellCache
  开放验证平台NutShell Cache验证案例
  ☆11Updated last month
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆62Updated 4 years ago
• Jpz-sdju / trinity
  ☆32Updated 5 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆92Updated last month
• OpenXiangShan / XS-Verilog-Library
  ☆47Updated 3 years ago
• XS-MLVP / env-xs-ov-00-bpu
  香山微架构开放验证第一期：昆明湖BPU模块UT测试模块及环境
  ☆30Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆73Updated 2 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆77Updated 2 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆224Updated 2 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆193Updated last year
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆138Updated 3 years ago