Pick your favorite language to verify your chip.
☆77Jan 30, 2026Updated last month
Alternatives and similar repositories for picker
Users that are interested in picker are comparing it to the libraries listed below
Sorting:
- A framework for building hardware verification platform using software method☆33Dec 24, 2025Updated 2 months ago
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆46Updated this week
- 开放验证平台NutShell Cache验证案例☆11Dec 2, 2025Updated 3 months ago
- ☆67Updated this week
- Open-source AI acceleration on FPGA: from ONNX to RTL☆49Jan 5, 2026Updated last month
- A gdbstub for connecting GDB to a RISC-V Debug Module☆30Oct 7, 2024Updated last year
- high-performance RTL simulator☆186Jun 19, 2024Updated last year
- Qemu tracing plugin using SimPoints☆17Sep 12, 2024Updated last year
- 香山微架构开放验证第一期:昆明湖BPU模块UT测试模块及环境☆30Oct 20, 2024Updated last year
- This repo includes XiangShan's function units☆30Feb 14, 2026Updated 2 weeks ago
- ☆17Mar 26, 2025Updated 11 months ago
- ☆93Feb 24, 2026Updated last week
- LLM Evaluation Benchmark on Hardware Formal Verification☆36Apr 3, 2025Updated 10 months ago
- 给NEMU移植Linux Kernel!☆22Jun 1, 2025Updated 9 months ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Oct 9, 2021Updated 4 years ago
- Using e-graphs for logic synthesis (ICCAD'25)☆32Updated this week
- ☆19Jan 2, 2026Updated 2 months ago
- Xiangshan deterministic workloads generator☆24May 14, 2025Updated 9 months ago
- The Scala parser to parse riscv/riscv-opcodes generate☆24Jan 21, 2026Updated last month
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- ☆21Jun 23, 2024Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- ☆19Dec 29, 2014Updated 11 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Jul 25, 2024Updated last year
- Tiny simple things inside the kernel☆27Jun 12, 2025Updated 8 months ago
- The Unified TileLink Memory Subsystem Tester for XiangShan☆12Jan 7, 2026Updated last month
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- RISC-V Matrix Specification☆23Dec 2, 2024Updated last year
- Build mini linux for your own RISC-V emulator!☆24Sep 11, 2024Updated last year
- A Heterogeneous GPU Platform for Chipyard SoC☆43Feb 23, 2026Updated last week
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆16Feb 17, 2026Updated 2 weeks ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated last year
- ☆12Dec 16, 2025Updated 2 months ago
- Generate Linux Perf event tables for Apple Silicon☆17Dec 16, 2025Updated 2 months ago
- ☆11Dec 23, 2025Updated 2 months ago
- ☆14Dec 27, 2024Updated last year
- RTLMeter benchmark suite☆29Updated this week
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆21Jul 24, 2025Updated 7 months ago