Alternatives and similar repositories for picker

Users that are interested in picker are comparing it to the libraries listed below

• XS-MLVP / toffee
  A framework for building hardware verification platform using software method
  ☆20Updated 2 weeks ago
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆35Updated this week
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• XS-MLVP / env-xs-ov-00-bpu
  香山微架构开放验证第一期：昆明湖BPU模块UT测试模块及环境
  ☆29Updated 8 months ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆27Updated 3 weeks ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 2 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 10 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• OpenXiangShan / GEM5
  ☆86Updated this week
• Jpz-sdju / trinity
  ☆24Updated 2 months ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• OSCPU / chisel-playground
  ☆67Updated 4 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆62Updated last year
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆27Updated 3 years ago
• Siudya / Nanhu
  Open-source high-performance RISC-V processor
  ☆29Updated 2 weeks ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆146Updated this week
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 7 months ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆55Updated 10 months ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆24Updated last month
• OpenXiangShan / XS-Verilog-Library
  ☆42Updated 3 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• sequencer / arithmetic
  ☆33Updated 3 months ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆64Updated last year
• loongson-community / open-la500
  Mirror of https://gitee.com/loongson-edu/open-la500.git
  ☆17Updated 5 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆88Updated last month