Alternatives and similar repositories for picker:

Users that are interested in picker are comparing it to the libraries listed below

• XS-MLVP / toffee
  a framework for building hardware verification platform using software method
  ☆14Updated 3 weeks ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 8 months ago
• OSCPU / yosys-sta
  ☆53Updated last month
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆28Updated 10 months ago
• OSCPU / ysyxSoC
  ☆79Updated this week
• OpenXiangShan / GEM5
  ☆74Updated this week
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆47Updated 2 years ago
• OSCPU / chisel-playground
  ☆59Updated last week
• ysyx-ta / ysyx-summer-readings
  ☆61Updated 6 months ago
• lizhirui / DreamCoreV2
  ☆21Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆54Updated last year
• OpenXiangShan / XS-Verilog-Library
  ☆38Updated 2 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆37Updated last year
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆57Updated last year
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆22Updated last year
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆137Updated 4 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 4 years ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆132Updated this week
• RV-BOSC / OpenNoC
  ☆114Updated this week
• OSCPU / ysyx-exam
  ☆20Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 11 months ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆30Updated 2 weeks ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆46Updated 3 months ago
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• pulp-platform / fpu
  ☆40Updated 5 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆57Updated last year
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆74Updated last week