OpenXiangShan / fudianLinks
Open source high performance IEEE-754 floating unit
☆86Updated last year
Alternatives and similar repositories for fudian
Users that are interested in fudian are comparing it to the libraries listed below
Sorting:
- Open-source high-performance non-blocking cache☆91Updated last week
- Vector Acceleration IP core for RISC-V*☆184Updated 6 months ago
- Chisel RISC-V Vector 1.0 Implementation☆118Updated last month
- chipyard in mill :P☆77Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆186Updated last month
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- Vector processor for RISC-V vector ISA☆130Updated 5 years ago
- (System)Verilog to Chisel translator☆117Updated 3 years ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆232Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆218Updated last week
- Open-source non-blocking L2 cache☆50Updated this week
- A dynamic verification library for Chisel.☆157Updated last year
- Verilog Configurable Cache☆185Updated last week
- high-performance RTL simulator☆182Updated last year
- Pure digital components of a UCIe controller☆75Updated last week
- A Fast, Low-Overhead On-chip Network☆232Updated 2 weeks ago
- Unit tests generator for RVV 1.0☆94Updated last month
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆59Updated 2 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆123Updated last week
- Generic Register Interface (contains various adapters)☆133Updated last month
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆67Updated last year
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆190Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆156Updated last year
- Advanced Architecture Labs with CVA6☆70Updated last year
- Pick your favorite language to verify your chip.☆72Updated this week