OpenXiangShan / xs-envLinks
XiangShan Frontend Develop Environment
☆68Updated last week
Alternatives and similar repositories for xs-env
Users that are interested in xs-env are comparing it to the libraries listed below
Sorting:
- Modern co-simulation framework for RISC-V CPUs☆171Updated this week
- Open-source high-performance non-blocking cache☆92Updated last month
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Updated 3 years ago
- ☆123Updated this week
- Pick your favorite language to verify your chip.☆77Updated last week
- Run rocket-chip on FPGA☆77Updated 2 months ago
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- ☆92Updated 4 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆161Updated 11 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆73Updated last year
- ☆70Updated 11 months ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆220Updated 2 months ago
- Open source high performance IEEE-754 floating unit☆89Updated last year
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- Comment on the rocket-chip source code☆179Updated 7 years ago
- RiVEC Bencmark Suite☆127Updated last year
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度 学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆78Updated 5 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆60Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆194Updated 4 months ago
- upstream: https://github.com/RALC88/gem5☆33Updated 2 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆78Updated last month
- "aura" my super-scalar O3 cpu core☆25Updated last year
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 2 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆110Updated 4 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆46Updated 2 years ago
- Advanced Architecture Labs with CVA6☆73Updated 2 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆138Updated 11 months ago
- Unit tests generator for RVV 1.0☆100Updated 2 months ago
- ☆90Updated 2 months ago
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆46Updated 2 months ago