Alternatives and similar repositories for xs-env:

Users that are interested in xs-env are comparing it to the libraries listed below

• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆80Updated 2 weeks ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆142Updated this week
• OpenXiangShan / GEM5
  ☆84Updated this week
• OSCPU / chisel-playground
  ☆67Updated 3 months ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆54Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆50Updated 2 years ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆153Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆65Updated 10 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆70Updated last year
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆52Updated 5 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆83Updated last month
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆132Updated 2 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆65Updated 9 months ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆196Updated this week
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆21Updated last week
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated last year
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆149Updated this week
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆49Updated this week
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆91Updated last month
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆139Updated 2 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 6 years ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆114Updated 5 months ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆62Updated this week
• mollybuild / RISCV-Measurement
  This is a repo for recording and reporting RISCV platform's test and measurement continuously.
  ☆59Updated last year
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• RV-BOSC / OpenNoC
  ☆153Updated last week
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆58Updated 3 years ago
• OSCPU / yosys-sta
  ☆63Updated 2 weeks ago