OpenXiangShan / xs-envLinks
XiangShan Frontend Develop Environment
☆64Updated this week
Alternatives and similar repositories for xs-env
Users that are interested in xs-env are comparing it to the libraries listed below
Sorting:
- Modern co-simulation framework for RISC-V CPUs☆147Updated this week
- Open-source high-performance non-blocking cache☆87Updated 2 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆150Updated 5 months ago
- Wrapper for Rocket-Chip on FPGAs☆135Updated 2 years ago
- ☆93Updated this week
- Pick your favorite language to verify your chip.☆60Updated this week
- Run rocket-chip on FPGA☆70Updated 8 months ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆51Updated 3 years ago
- ☆86Updated 3 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆69Updated last year
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- RiVEC Bencmark Suite☆118Updated 8 months ago
- Comment on the rocket-chip source code☆180Updated 6 years ago
- Unit tests generator for RVV 1.0☆89Updated 3 weeks ago
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆205Updated 2 months ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆104Updated 5 months ago
- ☆67Updated 5 months ago
- upstream: https://github.com/RALC88/gem5☆33Updated 2 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆41Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆171Updated 2 weeks ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆101Updated this week
- Open source high performance IEEE-754 floating unit☆83Updated last year
- Modeling Architectural Platform☆196Updated last week
- Vector processor for RISC-V vector ISA☆122Updated 4 years ago
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆77Updated 5 years ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆183Updated this week
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆218Updated 4 years ago
- Chisel Learning Journey☆109Updated 2 years ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆53Updated 4 years ago