Alternatives and similar repositories for xs-env

Users that are interested in xs-env are comparing it to the libraries listed below

• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆83Updated 3 weeks ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆146Updated this week
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆55Updated last year
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆75Updated last year
• OpenXiangShan / GEM5
  ☆86Updated this week
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆68Updated 11 months ago
• XUANTIE-RV / riscv-matrix-extension-spec
  A matrix extension proposal for AI applications under RISC-V architecture
  ☆148Updated 4 months ago
• OSCPU / chisel-playground
  ☆68Updated 4 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆134Updated 2 years ago
• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆88Updated last month
• OSCPU / ysyxSoC
  ☆86Updated last month
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆95Updated 2 months ago
• ucb-bar / hwacha
  Microarchitecture implementation of the decoupled vector-fetch accelerator
  ☆154Updated last year
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆31Updated 2 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆66Updated last year
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆202Updated last month
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆26Updated 2 weeks ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆53Updated 5 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆165Updated this week
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆63Updated this week
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆50Updated last week
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆102Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆102Updated 4 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆101Updated this week
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆121Updated 4 years ago