A collection of notes related to RISC-V before they are processed and digested
☆18Dec 19, 2017Updated 8 years ago
Alternatives and similar repositories for riscv-notes
Users that are interested in riscv-notes are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- This is my first trial project for designing RISC-V in Chisel☆17Apr 29, 2024Updated last year
- ☆12Feb 15, 2024Updated 2 years ago
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 3 months ago
- ☆18Jul 9, 2025Updated 8 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- Craft 2 top-level repository☆14May 15, 2019Updated 6 years ago
- Helper scripts used to clone RISC-V related git repos inside China.☆16Sep 17, 2020Updated 5 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Nov 13, 2020Updated 5 years ago
- Superscalar RISC-V processor written in Clash.☆35Aug 23, 2022Updated 3 years ago
- 4th RISC-V Workshop Tutorials☆13Jul 19, 2016Updated 9 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 3 years ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 7 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Nov 27, 2022Updated 3 years ago
- A collection of resources on modern C++☆10Jan 9, 2022Updated 4 years ago
- An SoC with multiple RISC-V IMA processors.☆19Aug 1, 2018Updated 7 years ago
- A prototype GUI for chisel-development☆51Jun 9, 2020Updated 5 years ago
- Memory System Microbenchmarks☆65Feb 9, 2023Updated 3 years ago
- ☆12May 20, 2021Updated 4 years ago
- Contains commonly used UVM components (agents, environments and tests).☆32Aug 17, 2018Updated 7 years ago
- 《关于浮点运算：作为程序员都应该了解什么？》☆27Apr 17, 2018Updated 7 years ago
- ☆26Sep 3, 2020Updated 5 years ago
- Repo for Source files of Avent miroZed Carrier Boards☆12Jan 9, 2025Updated last year
- ☆10Apr 8, 2021Updated 4 years ago
- My Work from The Elements of Computing Systems: Building a Modern Computer from First Principles☆17May 24, 2015Updated 10 years ago
- Redis is an in-memory database that persists on disk. The data model is key-value, but many different kind of values are supported: Strin…☆12Dec 26, 2020Updated 5 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 2 years ago
- Chisel/Firrtl execution engine☆155Aug 21, 2024Updated last year
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Jan 13, 2021Updated 5 years ago
- Advanced futures and promises in C++.☆17May 11, 2019Updated 6 years ago
- educational microarchitectures for risc-v isa☆67Feb 18, 2019Updated 7 years ago
- PyTorch Quantization Framework For OCP MX Datatypes.☆16May 30, 2025Updated 9 months ago
- Docker Containers and for building and verifiying RISC-V firmware☆11Aug 16, 2025Updated 7 months ago
- Python devicetree library☆16Oct 10, 2022Updated 3 years ago