A collection of notes related to RISC-V before they are processed and digested
☆18Dec 19, 2017Updated 8 years ago
Alternatives and similar repositories for riscv-notes
Users that are interested in riscv-notes are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 6 years ago
- Simple MIDAS Examples☆12Nov 25, 2018Updated 7 years ago
- ☆11Jan 21, 2019Updated 7 years ago
- Some notes on RISC-V☆37Jul 9, 2017Updated 8 years ago
- This is my first trial project for designing RISC-V in Chisel☆17Apr 29, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆12Feb 15, 2024Updated 2 years ago
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆20Nov 27, 2024Updated last year
- ☆25Apr 24, 2026Updated last week
- Wrappers for open source FPU hardware implementations.☆37Nov 27, 2025Updated 5 months ago
- ☆18Jul 9, 2025Updated 9 months ago
- Craft 2 top-level repository☆14May 15, 2019Updated 6 years ago
- Helper scripts used to clone RISC-V related git repos inside China.☆16Sep 17, 2020Updated 5 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Nov 13, 2020Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Superscalar RISC-V processor written in Clash.☆35Aug 23, 2022Updated 3 years ago
- 4th RISC-V Workshop Tutorials☆13Jul 19, 2016Updated 9 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 4 years ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 7 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Nov 27, 2022Updated 3 years ago
- An SoC with multiple RISC-V IMA processors.