Alternatives and similar repositories for GEM5:

Users that are interested in GEM5 are comparing it to the libraries listed below

• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆58Updated last year
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆41Updated 3 years ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆17Updated last month
• cry-daniel / Computer-Architecture-Learning
  ☆58Updated 2 years ago
• gem5 / gem5-resources
  The official repository for the gem5 resources sources.
  ☆63Updated last week
• OSCPU / ysyxSoC
  ☆79Updated last week
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆17Updated 6 years ago
• JamesAslan / MicroArchBench
  ☆64Updated 3 months ago
• gem5bootcamp / gem5-bootcamp-env
  The gem5 Bootcamp 2022 environment. Archived.
  ☆36Updated 7 months ago
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆27Updated 2 years ago
• OSCPU / chisel-playground
  ☆59Updated 2 weeks ago
• hpsresearchgroup / scarab
  Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator
  ☆72Updated 9 months ago
• Siudya / Nanhu
  Open-source high-performance RISC-V processor
  ☆27Updated last month
• dhschall / gem5-fdp
  Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5
  ☆16Updated this week
• Shuiliusheng / gem5_riscv_ckpt
  small and independent checkpoint
  ☆11Updated last year
• RV-BOSC / OpenNoC
  ☆114Updated last week
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆139Updated 4 months ago
• RALC88 / gem5
  This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…
  ☆20Updated 3 years ago
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆75Updated 4 years ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆16Updated last week
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆33Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆49Updated 2 years ago
• tukl-msd / gem5.TnT
  gem5 Tips & Tricks
  ☆66Updated 4 years ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆75Updated 2 weeks ago
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆110Updated 2 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆133Updated this week
• ysyx-ta / ysyx-summer-readings
  ☆61Updated 6 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 8 months ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆22Updated last year
• TeCSAR-UNCC / gem5-SALAM
  ☆90Updated last year